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公开(公告)号：US10601449B2
公开(公告)日：2020-03-24
申请号：US16575236
申请日：2019-09-18
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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公开(公告)号：US10033410B2
公开(公告)日：2018-07-24
申请号：US15206011
申请日：2016-07-08
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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Patent Agency Ranking
公开(公告)号：US10461781B2
公开(公告)日：2019-10-29
申请号：US16011483
申请日：2018-06-18
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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公开(公告)号：US10404289B1
公开(公告)日：2019-09-03
申请号：US15995036
申请日：2018-05-31
Applicant: INPHI CORPORATION
Inventor： Jamal Riani , Farshid Rafiee Rad , Benjamin Smith , Yu Liao , Sudeep Bhoja
Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
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公开(公告)号：US10374752B2
公开(公告)日：2019-08-06
申请号：US15693294
申请日：2017-08-31
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Jamal Riani , Arash Farhoodfar , Sudeep Bhoja
Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.
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公开(公告)号：US10326550B1
公开(公告)日：2019-06-18
申请号：US15691023
申请日：2017-08-30
Applicant: INPHI CORPORATION
Inventor： Jamal Riani , Benjamin Smith , Volodymyr Shvydun , Sudeep Bhoja
Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
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公开(公告)号：US09742594B2
公开(公告)日：2017-08-22
申请号：US15372051
申请日：2016-12-07
Applicant: INPHI CORPORATION
Inventor： Stephane Dallaire , Benjamin Smith
CPC classification number: H04L25/03006 , H04L7/027 , H04L25/03057 , H04L25/03885
Abstract: Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.
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