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公开(公告)号：US10664284B2
公开(公告)日：2020-05-26
申请号：US16289075
申请日：2019-02-28
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
Abstract: An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
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公开(公告)号：US09361116B2
公开(公告)日：2016-06-07
申请号：US13729915
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
Abstract translation: 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或表示无法执行命令的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。
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公开(公告)号：US11743761B2
公开(公告)日：2023-08-29
申请号：US17516460
申请日：2021-11-01
Applicant: INTEL CORPORATION
Inventor： Oren Kedem , Ran Mor , Nir Paz , Alon Pais , Dror Markovich , Igor Brainman
IPC: H04W28/02 , H04L1/1607 , H04L1/1829 , H04W8/22 , H04W28/04 , H04W28/22 , H04W28/06 , H04W84/12
CPC classification number: H04W28/0278 , H04L1/1671 , H04L1/1835 , H04W8/22 , H04W28/04 , H04W28/22 , H04W28/065 , H04W84/12
Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.
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公开(公告)号：US20220060936A1
公开(公告)日：2022-02-24
申请号：US17516460
申请日：2021-11-01
Applicant: INTEL CORPORATION
Inventor： Oren Kedem , Ran Mor , Nir Paz , Alon Pais , Dror Markovich , Igor Brainman
Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.
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公开(公告)号：US20210234596A1
公开(公告)日：2021-07-29
申请号：US17054256
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Wayne Ballantyne , Gregory Chance , Bruce Geren , Dror Markovich , Peter Pawliuk , Nebil Tanzi
IPC: H04B7/06 , H04B17/318 , H04B17/336 , H04W56/00
Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.
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Patent Agency Ranking
公开(公告)号：US10083037B2
公开(公告)日：2018-09-25
申请号：US15281944
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC: G06F9/38 , G06F9/30 , G06F11/07 , G06F9/54 , G06F12/0875
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.
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公开(公告)号：US10089113B2
公开(公告)日：2018-10-02
申请号：US15282082
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC: G06F9/38 , G06F9/30 , G06F11/07 , G06F9/54 , G06F12/0875
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.
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公开(公告)号：US11671866B2
公开(公告)日：2023-06-06
申请号：US17516460
申请日：2021-11-01
Applicant: INTEL CORPORATION
Inventor： Oren Kedem , Ran Mor , Nir Paz , Alon Pais , Dror Markovich , Igor Brainman
IPC: H04W28/02 , H04L1/1607 , H04L1/1829 , H04W8/22 , H04W28/04 , H04W28/22 , H04W28/06 , H04W84/12
CPC classification number: H04W28/0278 , H04L1/1671 , H04L1/1835 , H04W8/22 , H04W28/04 , H04W28/22 , H04W28/065 , H04W84/12
Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.
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公开(公告)号：US11329706B2
公开(公告)日：2022-05-10
申请号：US17054256
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Wayne Ballantyne , Gregory Chance , Bruce Geren , Dror Markovich , Peter Pawliuk , Nebil Tanzi
IPC: H04B7/06 , H04B17/318 , H04B17/336 , H04W56/00
Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.
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公开(公告)号：US20190196838A1
公开(公告)日：2019-06-27
申请号：US16289075
申请日：2019-02-28
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
CPC classification number: G06F9/3851 , G06F9/30079 , G06F9/3836 , G06F9/3855 , G06F9/3861 , G06F9/3877 , G06F9/46 , G06F15/7867 , G06F15/7892 , G06F15/80
Abstract: An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
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