公开(公告)号：US11743761B2

公开(公告)日：2023-08-29

申请号：US17516460

申请日：2021-11-01

Applicant: INTEL CORPORATION

Inventor： Oren Kedem ,  Ran Mor ,  Nir Paz ,  Alon Pais ,  Dror Markovich ,  Igor Brainman

IPC: H04W28/02 ,  H04L1/1607 ,  H04L1/1829 ,  H04W8/22 ,  H04W28/04 ,  H04W28/22 ,  H04W28/06 ,  H04W84/12

CPC classification number: H04W28/0278 ,  H04L1/1671 ,  H04L1/1835 ,  H04W8/22 ,  H04W28/04 ,  H04W28/22 ,  H04W28/065 ,  H04W84/12

Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.

公开(公告)号：US20220060936A1

公开(公告)日：2022-02-24

申请号：US17516460

申请日：2021-11-01

Applicant: INTEL CORPORATION

Inventor： Oren Kedem ,  Ran Mor ,  Nir Paz ,  Alon Pais ,  Dror Markovich ,  Igor Brainman

IPC: H04W28/02 ,  H04L1/16 ,  H04L1/18 ,  H04W28/04 ,  H04W28/22 ,  H04W8/22

Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.

公开(公告)号：US11671866B2

公开(公告)日：2023-06-06

申请号：US17516460

申请日：2021-11-01

Applicant: INTEL CORPORATION

Inventor： Oren Kedem ,  Ran Mor ,  Nir Paz ,  Alon Pais ,  Dror Markovich ,  Igor Brainman

IPC: H04W28/02 ,  H04L1/1607 ,  H04L1/1829 ,  H04W8/22 ,  H04W28/04 ,  H04W28/22 ,  H04W28/06 ,  H04W84/12

CPC classification number: H04W28/0278 ,  H04L1/1671 ,  H04L1/1835 ,  H04W8/22 ,  H04W28/04 ,  H04W28/22 ,  H04W28/065 ,  H04W84/12

Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second. STA an Ack including a buffer capacity field including the capacity value.

公开(公告)号：US20240220408A1

公开(公告)日：2024-07-04

申请号：US18089782

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Israel Diamand ,  Julius Mandelblat ,  Asaf Rubinstein ,  Igor Brainman

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1016

Abstract: Methods and apparatus relating to dynamic allocation schemes applied to a memory side cache for bandwidth and/or performance optimization are described. In an embodiment, a memory side cache stores a portion of data to be stored in a main memory. Logic circuitry determines whether to allocate a portion of the memory side cache for use by a device. The remaining portion of the memory side cache is to be used by a processor. The allocated portion of the memory side cache is reallocated for use by the processor in response to a determination that the allocated portion of the memory side cache is no longer to be used by the device. Other embodiments are also disclosed and claimed.