公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.