公开(公告)号：US10665499B2

公开(公告)日：2020-05-26

申请号：US16021352

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Miriam R. Reshotko ,  Nafees A. Kabir ,  Manish Chandhok

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522 ,  H01L23/482

Abstract: An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.

公开(公告)号：US20230230919A1

公开(公告)日：2023-07-20

申请号：US17579249

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Nafees A. Kabir ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5228 ,  H01L21/76825

Abstract: An integrated circuit device includes a first interconnect layer, and a conductive first interconnect feature and a conductive second interconnect feature laterally separated by a body of insulating or semiconductor material. In an example, the first and second interconnect features are above the first interconnect layer. The integrated circuit device further includes a non-conductive feature above and on the first interconnect feature, and a conductive third interconnect feature above and on the second interconnect feature. The integrated circuit device also includes a second interconnect layer above the non-conductive feature and third interconnect features. In an example, the second and third interconnect features conductively couple the first and second interconnect layers.

公开(公告)号：US11462469B2

公开(公告)日：2022-10-04

申请号：US16143700

申请日：2018-09-27

Applicant: INTEL CORPORATION

Inventor： Kevin L. Lin ,  Nafees A. Kabir ,  Richard Schenker

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.

公开(公告)号：US20220084942A1

公开(公告)日：2022-03-17

申请号：US17017735

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Christopher J. Jezewski ,  Manish Chandhok ,  Nafees A. Kabir ,  Matthew V. Metz

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.