公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

公开(公告)号：US12237223B2

公开(公告)日：2025-02-25

申请号：US17033483

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Charles H. Wallace ,  Manish Chandhok ,  Mohit K Haran ,  Gurpreet Singh ,  Eungnak Han ,  Florian Gstrein ,  Richard E. Schenker ,  David Shykind ,  Jinnie Aloysius ,  Sean Pursel

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L27/088

Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

公开(公告)号：US20240360264A1

公开(公告)日：2024-10-31

申请号：US18766426

申请日：2024-07-08

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240204083A1

公开(公告)日：2024-06-20

申请号：US18066307

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  Florian Gstrein ,  Charles Henry Wallace ,  Eungnak Han ,  Leonard P. Guler

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L29/6656 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L29/66545 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2924/15311

Abstract: DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.

公开(公告)号：US12002678B2

公开(公告)日：2024-06-04

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20240088218A1

公开(公告)日：2024-03-14

申请号：US17943443

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Leonard P. Guler ,  Gurpreet Singh ,  Manish Chandhok ,  Matthew J. Prince

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices. Subsequent processes allow neighboring gate or source or drain regions connections.

公开(公告)号：US12230536B1

公开(公告)日：2025-02-18

申请号：US17559490

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Manish Chandhok ,  Gurpreet Singh

IPC: H01L21/768 ,  H01L23/522

Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US20240194672A1

公开(公告)日：2024-06-13

申请号：US18064362

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Bharath Bangalore Rajeeva ,  Manish Chandhok ,  Gurpreet Singh ,  Kevin Huggins ,  Eungnak Han ,  Florian Gstrein ,  Marko Radosavljevic

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L23/522 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0271 ,  H01L23/5226 ,  H01L29/1033 ,  H01L29/42364

Abstract: An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.