公开(公告)号：US20220199462A1

公开(公告)日：2022-06-23

申请号：US17511693

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Florian Gstrein ,  Eungnak Han ,  Marie Krysak ,  Tayseer Mahdi ,  Xuanxuan Chen ,  Brandon Jay Holybee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US20220199540A1

公开(公告)日：2022-06-23

申请号：US17125232

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Marie Krysak ,  Brandon Jay Holybee ,  Florian Gstrein

IPC: H01L23/538

Abstract: Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.

公开(公告)号：US20210375745A1

公开(公告)日：2021-12-02

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: H01L23/528 ,  H01L23/522

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.