公开(公告)号：US12237388B2

公开(公告)日：2025-02-25

申请号：US17123828

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Changyok Park ,  Guillaume Bouche ,  Hyuk Ju Ryu ,  Charles Henry Wallace ,  Mohit K. Haran

IPC: H01L29/423 ,  H01L21/768 ,  H01L25/065 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：US20240096785A1

公开(公告)日：2024-03-21

申请号：US17933000

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： June Choi ,  Charles Henry Wallace ,  Richard E. Schenker ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242

Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.

公开(公告)号：US20220102148A1

公开(公告)日：2022-03-31

申请号：US17033228

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Charles Henry Wallace ,  Mohit K. Haran ,  Paul A. Nyhus ,  Gurpreet Singh ,  Eungnak Han ,  David Nathan Shykind ,  Sean Michael Pursel

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

公开(公告)号：US20240203869A1

公开(公告)日：2024-06-20

申请号：US18067031

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Nikhil Jasvant Mehta ,  Charles Henry Wallace

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76892 ,  H01L23/53228 ,  H01L23/53257

Abstract: Methods for fabricating an integrated circuit (IC) device with one or more hybrid metal lines are provided. An example IC device includes a substrate; and a metal line extending, along an axis, over the substrate. The metal line has a first end and a second end along the axis. A portion of the metal line at the first end includes a first electrically conductive material. Another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. In some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.

公开(公告)号：US11652045B2

公开(公告)日：2023-05-16

申请号：US17511656

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/5329

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20210183761A1

公开(公告)日：2021-06-17

申请号：US16713867

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Reken Patel ,  Mohit K. Haran ,  Jeremy J. Guttman ,  Shyam B. Kadali ,  Ruth Amy Brain ,  Seyedhamed M Barghi ,  Zhenjun Zhang ,  James Jeong ,  Robert M. Bigwood ,  Charles Henry Wallace

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.

公开(公告)号：US20210082805A1

公开(公告)日：2021-03-18

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

公开(公告)号：US20220199420A1

公开(公告)日：2022-06-23

申请号：US17124730

申请日：2020-12-17

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Eungnak Han ,  Manish Chandhok ,  Richard E. Schenker ,  Florian Gstrein ,  Paul A. Nyhus ,  Charles Henry Wallace

IPC: H01L21/311 ,  H01L21/768

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：US20220130721A1

公开(公告)日：2022-04-28

申请号：US17076870

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Shashi Vyas ,  Akm Shaestagir Chowdhury ,  Andy Chih-Hung Wei ,  Charles Henry Wallace

IPC: H01L21/768 ,  H01L23/522

Abstract: Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6.