公开(公告)号：US20220148981A1

公开(公告)日：2022-05-12

申请号：US17579417

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Ananth PRABHAKUMAR ,  Krishna SRINIVASAN ,  Arnab SARKAR

IPC: H01L23/00 ,  H01L23/525

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

公开(公告)号：US20180182696A1

公开(公告)日：2018-06-28

申请号：US15900696

申请日：2018-02-20

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20190295961A1

公开(公告)日：2019-09-26

申请号：US15934191

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Ananth PRABHAKUMAR ,  Krishna SRINIVASAN ,  Arnab SARKAR

IPC: H01L23/00 ,  H01L23/525

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

公开(公告)号：US20190172778A1

公开(公告)日：2019-06-06

申请号：US16261475

申请日：2019-01-29

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/50

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20160284635A1

公开(公告)日：2016-09-29

申请号：US15174921

申请日：2016-06-06

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract translation: 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。