公开(公告)号：US20240030116A1

公开(公告)日：2024-01-25

申请号：US18375133

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/29

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20230307441A1

公开(公告)日：2023-09-28

申请号：US17706454

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Ahmed ABOU-ALFOTOUH ,  Jonathan DOUGLAS ,  Alan WU ,  Nachiket Venkappayya DESAI ,  Han Wui THEN ,  Harish KRISHNAMURTHY ,  Kaladhar RADHAKRISHNAN ,  Sanka GANESAN ,  Krishnan RAVICHANDRAN

IPC: H01L27/06 ,  H05K1/18 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L49/02 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H05K1/181 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L28/10 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H05K2201/1003 ,  H05K2201/10734

Abstract: Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

公开(公告)号：US20200273784A1

公开(公告)日：2020-08-27

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20250029929A1

公开(公告)日：2025-01-23

申请号：US18907985

申请日：2024-10-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20220344247A1

公开(公告)日：2022-10-27

申请号：US17862300

申请日：2022-07-11

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20210082826A1

公开(公告)日：2021-03-18

申请号：US17102726

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Vipul Vijay MEHTA ,  Eric Jin LI ,  Sanka GANESAN ,  Debendra MALLIK ,  Robert Leon SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20200006293A1

公开(公告)日：2020-01-02

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert SANKMAN ,  Sanka GANESAN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Lizabeth KESER

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US20180331043A1

公开(公告)日：2018-11-15

申请号：US15774257

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Zhiguo QIAN ,  Kemal AYGUN ,  Yidnekachew S. MEKONNEN ,  Gregorio R. MURTAGIAN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Jeff C. MORRISS

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/552

CPC classification number: H01L23/5384 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/00 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

公开(公告)号：US20250070030A1

公开(公告)日：2025-02-27

申请号：US18943420

申请日：2024-11-11

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Ram VISWANATH ,  Xavier Francois BRUN ,  Tarek A. IBRAHIM ,  Jason M. GAMBA ,  Manish DUBEY ,  Robert Alan MAY

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20230207475A1

公开(公告)日：2023-06-29

申请号：US17561580

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Sanka GANESAN ,  Debendra MALLIK

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L25/0657 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include chiplet modules and die modules. In an embodiment, a chiplet module comprises a first chiplet, where the first chiplet comprises a first active surface. In an embodiment the chiplet module further comprises a second chiplet, where the second chiplet comprises a second active surface. In an embodiment, the chiplet module further comprises a hybrid bonding interface between the first chiplet and the second chiplet, where the hybrid bonding interface electrically couples the first chiplet to the second chiplet.