公开(公告)号：US20230260884A1

公开(公告)日：2023-08-17

申请号：US18138512

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/544 ,  H01L22/32 ,  H01L23/585 ,  H01L25/0655 ,  H01L24/10 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512 ,  H01L24/16 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20220148981A1

公开(公告)日：2022-05-12

申请号：US17579417

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Ananth PRABHAKUMAR ,  Krishna SRINIVASAN ,  Arnab SARKAR

IPC: H01L23/00 ,  H01L23/525

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

公开(公告)号：US20180226331A1

公开(公告)日：2018-08-09

申请号：US15749465

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/58 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/10 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20250029908A1

公开(公告)日：2025-01-23

申请号：US18904780

申请日：2024-10-02

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20200066640A1

公开(公告)日：2020-02-27

申请号：US15774512

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Ravindranath V. MAHAJAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments are generally directed to hybrid technology 3-D die stacking. An embodiment of an apparatus includes a TSV array substrate including through silicon vias (TSVs) and wire bond contacts; a stack of one or more wire bond dies; and a package coupled with the TSV substrate by a first interconnect, wherein the one or more wire bond dies are connected via one or more wires to one or more wire bond contacts of the TSV array substrate, and wherein the TSV array substrate provides connections to the for each of the one or more wire bond dies.

公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

公开(公告)号：US20220130743A1

公开(公告)日：2022-04-28

申请号：US17573479

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20190295961A1

公开(公告)日：2019-09-26

申请号：US15934191

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Ananth PRABHAKUMAR ,  Krishna SRINIVASAN ,  Arnab SARKAR

IPC: H01L23/00 ,  H01L23/525

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.