公开(公告)号：US20180248004A1

公开(公告)日：2018-08-30

申请号：US15753739

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/30

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20200286996A1

公开(公告)日：2020-09-10

申请号：US16876528

申请日：2020-05-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20180248015A1

公开(公告)日：2018-08-30

申请号：US15754874

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  MARK R. BRAZIER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  OWEN Y. LOH

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/517 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.