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公开(公告)号：US20200333859A1
公开(公告)日：2020-10-22
申请号：US16946739
申请日：2020-07-02
Applicant: Intel Corporation
Inventor： Michael D. Nelson , Jawad B. Khan , Randall K. Webb , Knut S. Grimsrud , Wayne J. Allen
Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.
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公开(公告)号：US11604594B2
公开(公告)日：2023-03-14
申请号：US17390441
申请日：2021-07-30
Applicant: Intel Corporation
Inventor： Divya Narayanan , Jawad B. Khan , Michael D. Nelson , Akshay G. Pethe
IPC: G06F3/06
Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.
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3.发明授权公开(公告)号：US10721832B2
公开(公告)日：2020-07-21
申请号：US16083411
申请日：2016-03-14
Applicant: Intel Corporation
Inventor： Michael D. Nelson , Jawad B. Khan , Randall K. Webb
Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.
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公开(公告)号：US11385689B2
公开(公告)日：2022-07-12
申请号：US16343741
申请日：2016-10-26
Applicant: INTEL CORPORATION
Inventor： Jawad B. Khan , Andrew Warrack Morning-Smith , John Hung , Michael D. Nelson , Craig J. Jahne
Abstract: An integrated electronic card front EMI cage and latch is described that is suitable for use in a data storage system. In an example a latch module for an electronic component housing has a latch housing having an arm with an attachment point to fasten the latch housing to an end of the housing and an EMI cage having a front body and a plurality of fingers extending from the front body, the front body being held to the end of the housing by the latch housing and the fingers being configured to be outside an exterior of the housing on at least two sides of the housing to block electromagnetic interference from passing along the at least two sides of the housing.
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公开(公告)号：US11079958B2
公开(公告)日：2021-08-03
申请号：US16383490
申请日：2019-04-12
Applicant: INTEL CORPORATION
Inventor： Divya Narayanan , Jawad B. Khan , Michael D. Nelson , Akshay G. Pethe
IPC: G06F3/06
Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.
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Patent Agency Ranking
公开(公告)号：US20210082875A1
公开(公告)日：2021-03-18
申请号：US16573266
申请日：2019-09-17
Applicant: INTEL CORPORATION
Inventor： Michael D. Nelson
IPC: H01L25/065 , H01L25/18 , H01L23/525
Abstract: A semiconductor die includes one or more semiconductor devices (e.g., memory array, processors), first and second banks of I/O ports arranged along one or more sides of the die, and a multiplexing circuit. The multiplexing circuit can be changed between a first state and a second state. In the first state the first bank of I/O ports is coupled to the semiconductor device(s) and the second bank of I/O ports is not coupled to the semiconductor device(s), and in the second state the first bank of I/O ports is not coupled to the semiconductor device(s) and the second bank of I/O ports is coupled to the semiconductor device(s). The state of the multiplexing circuit can be set, for example, by an on-die fuse circuit or an externally accessible select line. The semiconductor die can be included in a chip package, which can be included on a printed circuit board.
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公开(公告)号：US11139273B2
公开(公告)日：2021-10-05
申请号：US16573266
申请日：2019-09-17
Applicant: INTEL CORPORATION
Inventor： Michael D. Nelson
IPC: H01L25/065 , H01L25/18 , H01L23/525
Abstract: A semiconductor die includes one or more semiconductor devices (e.g., memory array, processors), first and second banks of I/O ports arranged along one or more sides of the die, and a multiplexing circuit. The multiplexing circuit can be changed between a first state and a second state. In the first state the first bank of I/O ports is coupled to the semiconductor device(s) and the second bank of I/O ports is not coupled to the semiconductor device(s), and in the second state the first bank of I/O ports is not coupled to the semiconductor device(s) and the second bank of I/O ports is coupled to the semiconductor device(s). The state of the multiplexing circuit can be set, for example, by an on-die fuse circuit or an externally accessible select line. The semiconductor die can be included in a chip package, which can be included on a printed circuit board.
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公开(公告)号：US10530077B2
公开(公告)日：2020-01-07
申请号：US15807519
申请日：2017-11-08
Applicant: INTEL CORPORATION
Inventor： Jawad B. Khan , Jorge Ulises Martinez Araiza , Michael D. Nelson
Abstract: Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity further includes a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB.
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公开(公告)号：US09904336B1
公开(公告)日：2018-02-27
申请号：US15373631
申请日：2016-12-09
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Randall K. Webb , Michael D. Nelson
IPC: G06F1/20
CPC classification number: G06F1/206
Abstract: A data storage system is described with an array of front fans and moving doors for airflow control. In one example an enclosure is configured to mount in a rack. A horizontal plane board in the enclosure has memory connectors aligned in a row and external interfaces. Memory cards connect to a respective memory connector of the board. Removable fans at the front of the enclosure push air along the memory cards to the rear and doors at the front of the enclosure, each have an open position to accommodate a corresponding fan and a closed position to block airflow when the corresponding fan is removed.
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10.发明授权公开(公告)号：US11102902B2
公开(公告)日：2021-08-24
申请号：US16932635
申请日：2020-07-17
Applicant: Intel Corporation
Inventor： Michael D. Nelson , Jawad B. Khan , Randall K. Webb
Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.
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