-
公开(公告)号：US09042652B2
公开(公告)日：2015-05-26
申请号：US13666913
申请日：2012-11-01
Applicant: Intel Corporation
Inventor： Niraj Gupta , Oren Agam , Benny Eitan , Mostafa Hagog
CPC classification number: G06K9/4638 , G06T7/11 , G06T7/187 , G06T2200/28
Abstract: An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.
Abstract translation: 装置可以包括存储器，处理器电路和连接的部件标签模块。 连接的组件标注模块可操作于处理器电路，以在从存储器读取包括多个像素的图像的读取期间确定一个或多个连接的组件，将标签分配给多个像素的多个像素，生成一个或多个 针对相应的一个或多个标签的更多标签连接，每个标签连接将较高标签链接到相同连接部件的最低标签，并且向该存储器写入一个或多个标签的每个标签，该标签由标签定义 将标签分配给每个像素后，每个标签的连接。
-
公开(公告)号：US11494194B2
公开(公告)日：2022-11-08
申请号：US17216618
申请日：2021-03-29
Applicant: Intel Corporation
Inventor： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
-
公开(公告)号：US10963263B2
公开(公告)日：2021-03-30
申请号：US16059001
申请日：2018-08-08
Applicant: Intel Corporation
Inventor： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
-
4.发明授权公开(公告)号：US10303471B2
公开(公告)日：2019-05-28
申请号：US15445741
申请日：2017-02-28
Applicant: Intel Corporation
Inventor： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
-
公开(公告)号：US10061593B2
公开(公告)日：2018-08-28
申请号：US15426276
申请日：2017-02-07
Applicant: Intel Corporation
Inventor： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
CPC classification number: G06F9/3887 , G06F9/30076 , G06F9/3879 , G06F15/8007
Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
-
Patent Agency Ranking
公开(公告)号：US20150077422A1
公开(公告)日：2015-03-19
申请号：US14550214
申请日：2014-11-21
Applicant: INTEL CORPORATION
Inventor： Alon Gluska , Niraj Gupta , Mostafa Hagog , Dror Reif
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
Abstract translation: 洪水填充技术和结构被公开。 根据一个实施例，该架构包括具有软件接口的硬件原语，该软件接口在执行洪水填充处理时共同允许基于数据和基于任务的并行性。 硬件原语被定义为执行洪水填充功能并且是可扩展的，并且可以在一些实施例中以可以调整以满足功率/性能目标的按位定义来实现。 在执行洪水填充操作时，并且根据示例性实施例，软件接口产生并行线程并将其发布到处理元件，使得每个线程可以独立运行直到完成。 每个处理元件依次访问洪水填充硬件图元，每个填充硬件图元被配置为在N×M图像块内淹没种子。 在某些情况下，根据仲裁方案，可以对洪水填充硬件原语的处理单元命令进行排队和执行。
-
公开(公告)号：US12086603B2
公开(公告)日：2024-09-10
申请号：US17975596
申请日：2022-10-27
Applicant: Intel Corporation
Inventor： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
CPC classification number: G06F9/3887 , G06F9/30076 , G06F9/3879 , G06F15/8007
Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
-
公开(公告)号：US08902238B2
公开(公告)日：2014-12-02
申请号：US13651854
申请日：2012-10-15
Applicant: Intel Corporation
Inventor： Alon Gluska , Niraj Gupta , Mostafa Hagog , Dror Reif
CPC classification number: G06T1/20
Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
Abstract translation: 洪水填充技术和结构被公开。 根据一个实施例，该架构包括具有软件接口的硬件原语，该软件接口在执行洪水填充处理时共同允许基于数据和基于任务的并行性。 硬件原语被定义为执行洪水填充功能并且是可扩展的，并且可以在一些实施例中以可以调整以满足功率/性能目标的按位定义来实现。 在执行洪水填充操作时，并且根据示例性实施例，软件接口产生并行线程并将其发布到处理元件，使得每个线程可以独立运行直到完成。 每个处理元件依次访问洪水填充硬件图元，每个填充硬件图元被配置为在N×M图像块内淹没种子。 在某些情况下，根据仲裁方案，可以对洪水填充硬件原语的处理单元命令进行排队和执行。
-
公开(公告)号：US10901748B2
公开(公告)日：2021-01-26
申请号：US16149050
申请日：2018-10-01
Applicant: Intel Corporation
Inventor： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
-
公开(公告)号：US09972062B2
公开(公告)日：2018-05-15
申请号：US14550214
申请日：2014-11-21
Applicant: INTEL CORPORATION
Inventor： Alon Gluska , Niraj Gupta , Mostafa Hagog , Dror Reif
CPC classification number: G06T1/20
Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.019 seconds)
