公开(公告)号：US20190109234A1

公开(公告)日：2019-04-11

申请号：US16199445

申请日：2018-11-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L29/167 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/45 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20180197789A1

公开(公告)日：2018-07-12

申请号：US15576396

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  YING PANG ,  NABIL G. MISTKAWI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  HUANG-LIN CHAO

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/6681

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US20180145174A1

公开(公告)日：2018-05-24

申请号：US15860292

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20170012124A1

公开(公告)日：2017-01-12

申请号：US15116453

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

Abstract translation: 公开了用于改善锗（Ge）富集的p-MOS源极/漏极触点的集成的技术，例如降低接触电阻。 这些技术包括将p型富锗层直接沉积在接触沟槽位置的硅（Si）表面上，因为Si表面有利于沉积高质量的导电富Ge材料。 在一个示例性方法中，在去除先前沉积在源极/漏极位置中的牺牲硅锗（SiGe）层之后，在源/漏接触沟槽位置中的富Si层沉积在Si衬底的表面上。 在另一示例性方法中，富集层沉积在接触沟槽位置的Si包覆层上，其中Si包覆层沉积在功能性p型SiGe层上。 在一些情况下，富锗层包含至少50％的Ge（并且可以含有锡（Sn）和/或Si），并且是以高于1E20cm-3的掺杂的硼（B）。