公开(公告)号：US20240004709A1

公开(公告)日：2024-01-04

申请号：US17809968

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kshitij A. DOSHI ,  Rita H. WOUHAYBI ,  Francesc GUIM BERNAT ,  Marcos CARRANZA

IPC: G06F9/50

CPC classification number: G06F9/5005

Abstract: Examples relate to a concept for software application container hardware resource allocation, and in particular to sidecar apparatuses, sidecar devices, methods for a software application container sidecars, a resource management controller apparatus, a resource management controller device, and corresponding computer programs and computer systems. A sidecar apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to obtain information on hardware resources desired by a software application container from the software application container, and to provide a request for changing the hardware resources allocated to the software application container to another entity capable of influencing an allocation of hardware resources to the software application container.

公开(公告)号：US20230350722A1

公开(公告)日：2023-11-02

申请号：US18145057

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06F9/52

Abstract: An apparatus is proposed, the apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to receive a request to execute a task on a computing system, receive a service-level agreement, SLA, indicating at least one of a desired computing performance and a desired computing power for an execution of the task by the computing system, determine an interdependency between at least two resources of the computing system required for the execution of the task based on the SLA and schedule the execution of the task based on the interdependency between the at least two resources.

公开(公告)号：US20230118160A1

公开(公告)日：2023-04-20

申请号：US18068531

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN

IPC: G06F11/07 ,  G06F8/65 ,  G06F9/22

Abstract: Examples of the present disclosure relate to an apparatus, device, method, and computer program for monitoring a processing device from a trusted domain. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to receive a request for monitoring the processing device from the trusted domain; authenticate the request; obtain information on a failure report related to a component of the processing device, with a possible failure having occurred at runtime of the processing device; and provide the information on the failure report in the trusted domain.

公开(公告)号：US20220219324A1

公开(公告)日：2022-07-14

申请号：US17709493

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Vinayak HONKOTE ,  Rajesh POORNACHANDRAN ,  Nikhilesh Kumar SINGH

IPC: B25J9/16

Abstract: A safety system includes a robot, the robot comprising, a function module, configured to perform a robot function; and
a safety module, configured to communicate with the robot, the safety module comprising a stimulus-response tester, configured to send a stimulus of a stimulus-response pair, comprising a stimulus and an expected response to the stimulus, to the robot for processing by the function module; and receive from the function module a response representing the processed stimulus; wherein if a difference between the response and the expected response is within a predetermined range, the safety module is configured to operate according to a first operational mode; and if the difference between the response and the expected response is outside of the predetermined range, the safety module is configured to operate according to a second operational mode.

公开(公告)号：US20240143329A1

公开(公告)日：2024-05-02

申请号：US17934580

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Mingqiu SUN ,  Vincent ZIMMER ,  Rajesh POORNACHANDRAN ,  Gopinatth SELVARAJE

IPC: G06F9/30 ,  G06F9/455 ,  G06F21/57

CPC classification number: G06F9/30181 ,  G06F9/45508 ,  G06F21/57

Abstract: Various examples relate to an apparatus, device, method, and computer program for extending instructions sup-ported by a processor. The apparatus is configured to identify at least a part of a computer program targeting an instruction unsupported by a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor. The apparatus is configured to extend the instructions supported by the processor, based on the targeted unsupported instruction. The apparatus is configured to execute the computer program.

公开(公告)号：US20240126587A1

公开(公告)日：2024-04-18

申请号：US18394677

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Mona MINAKSHI ,  Shamima NAJNIN ,  Rajesh POORNACHANDRAN

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45591

Abstract: Examples relate to an apparatus, a device, a method, a computer program (or computer-readable medium) and computer system for determining presence of a noisy neighbor virtual machine. Some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain performance information of one or more hardware performance measurement components of the computer system, determine, based on the performance information, a deviation of a utilization of the computer system from an expected utilization of the computer system, and determine presence of a first virtual machine having a workload that impacts a performance of one or more second virtual machines based on the deviation.

公开(公告)号：US20240013181A1

公开(公告)日：2024-01-11

申请号：US18474278

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Marcos CARRANZA ,  Mallikarjuna CHILAKALA ,  Francesc GUIM BERNAT ,  Karthik KUMAR

IPC: G06Q20/14 ,  G06Q20/38 ,  G06Q50/06

CPC classification number: G06Q20/145 ,  G06Q20/38215 ,  G06Q50/06

Abstract: Various examples relate to apparatuses, devices, methods and computer programs for a group leader and a group member of a group of nodes of a blockchain network. The apparatus for the group leader comprises interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to manage a membership of nodes of the blockchain network in the group of nodes, perform or delegate blockchain-related computational activity on behalf of the group of nodes according to an energy criterion.

公开(公告)号：US20230421374A1

公开(公告)日：2023-12-28

申请号：US17809297

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kshitij A. DOSHI ,  Rita H. WOUHAYBI ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos CARRANZA ,  Cesar MARTINEZ SPESSOT

IPC: H04L9/30 ,  H04L9/32

CPC classification number: H04L9/30 ,  H04L9/3247

Abstract: Examples relate to a computer system, a telemetry hub apparatus, a telemetry hub device, a telemetry hub method, a microservice apparatus, a microservice device, a microservice method and to corresponding computer programs. The telemetry apparatus is configured to obtain telemetry information from a plurality of microservices, and to provide access to the telemetry information for the plurality of microservices according to an access scheme.

公开(公告)号：US20220326962A1

公开(公告)日：2022-10-13

申请号：US17847166

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Navneeth JAYARAJ ,  Richard Marian THOMAIYAR ,  Ashraf JAVEED ,  Vikas MISHRA ,  Rajesh POORNACHANDRAN ,  Mahammad Yaseen Isasaheb MULLA ,  Laxminarayan KAMATH ,  Karunakara KOTARY ,  Dustin FREDRICKSON

IPC: G06F9/4401 ,  G06F1/28

Abstract: An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.

公开(公告)号：US20220083398A1

公开(公告)日：2022-03-17

申请号：US17532609

申请日：2021-11-22

Applicant: Intel Corporation

Inventor： Binuraj RAVINDRAN ,  George S. POWLEY ,  Rajesh POORNACHANDRAN

IPC: G06F9/50

Abstract: A system can dynamically apply compression to data storage for workloads based on how the compression affects the performance for the workloads. The system can track a service level indicator (SLI) during runtime of a workload and dynamically change a level of compression for the workload based on the SLI. The system can track the SLI to increase compression for the workload while maintaining a performance minimum specified in a service level agreement (SLA) for the workload.