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1.
公开(公告)号:US20180276124A1
公开(公告)日:2018-09-27
申请号:US15465513
申请日:2017-03-21
Applicant: INTEL CORPORATION
Inventor: Wei CHEN , Rajat AGARWAL , Jing LING , Daniel W. LIU
IPC: G06F12/0808 , G06F12/0811 , G06F1/32 , G06F3/06 , G06F12/128 , G06F12/06
CPC classification number: G06F12/0808 , G06F1/3287 , G06F3/0685 , G06F12/0638 , G06F12/0811 , G06F12/0866 , G06F12/0868 , G06F12/12 , G06F12/128 , G06F2212/205 , G06F2212/283 , G06F2212/621
Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.
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2.
公开(公告)号:US20190171568A1
公开(公告)日:2019-06-06
申请号:US16258486
申请日:2019-01-25
Applicant: INTEL CORPORATION
Inventor: Wei CHEN , Rajat AGARWAL , Jing LING , Daniel W. LIU
IPC: G06F12/0808 , G06F12/0866 , G06F12/06 , G06F12/128 , G06F12/0811 , G06F1/3287 , G06F3/06 , G06F12/0868
Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.
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