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公开(公告)号：US12271319B2
公开(公告)日：2025-04-08
申请号：US17054762
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Yanjie Pan , Yong Jiang , Yuanyuan Li , Yong Zhang
IPC: G06F12/123 , G06F5/06 , G06F5/12 , G06F12/0893
Abstract: Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.
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公开(公告)号：US10949251B2
公开(公告)日：2021-03-16
申请号：US16066652
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Yong Jiang , Yuanyuan Li , Jianghong Du , Kuilin Chen , Thomas A. Tetzlaff
Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
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公开(公告)号：US10832430B2
公开(公告)日：2020-11-10
申请号：US16463456
申请日：2016-12-23
Applicant: INTEL CORPORATION
Inventor： Yi Wu , Shaojun Yao , Yong Jiang
IPC: G06T7/557 , H04N13/271 , H04N13/218 , H04N13/00
Abstract: A system for sub-pixel disparity estimation is described herein. The system includes a plenoptic camera, a memory, and a processor. The memory is configured to store imaging data. The processor is \coupled to the memory and the plenoptic camera. The processor is to obtain a plurality of sub-aperture views, select a subset of sub-aperture views as reference views for a disparity calculation, and calculate an integer disparity for the reference views. The processor is also to refine the integer disparity to sub-pixel disparity accuracy for the reference views and propagate the sub-pixel disparity from the reference views to other views of the plurality of sub-aperture views.
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公开(公告)号：US20200320196A1
公开(公告)日：2020-10-08
申请号：US16650643
申请日：2017-12-13
Applicant: INTEL CORPORATION
Inventor： Danyu Bi , Salmin Sultana , Yuanyuan Li , Yong Jiang , Pramod Pesara , Selvakumar Panneer , Ravi Sahita
IPC: G06F21/56 , G06F9/30 , G06F9/448 , G06F11/36 , G06F12/1009
Abstract: A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (202). The processor can also detect an invalid indirect branch instruction from the processor trace information (204) and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (206). Additionally, the processor can block the application from accessing or modifying memory (208).
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公开(公告)号：US20190042412A1
公开(公告)日：2019-02-07
申请号：US15757727
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Jianghong Du , Yong Jiang , Lei Shen , Yuanyuan Li , Ruijia Li , Lingyi Kong
IPC: G06F12/084
Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20240370372A1
公开(公告)日：2024-11-07
申请号：US18763009
申请日：2024-07-03
Applicant: Intel Corporation
Inventor： Xiaodong Qiu , Yong Jiang , Changwon Rhee , Cui Tang , Shuangpeng Zhou , Lei Chen , Danyu Bi , Peiqing Jiang , Chengxi Wu
IPC: G06F12/084 , G06F9/48
Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.
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公开(公告)号：US11550632B2
公开(公告)日：2023-01-10
申请号：US15775249
申请日：2015-12-24
Applicant: INTEL CORPORATION
Inventor： Yuanyuan Li , Yong Jiang , Linghyi Kong
Abstract: A mechanism is described for facilitating efficient communication and data processing across clusters of computing machines in a heterogenous computing environment. A method includes detecting a request for processing of data using a programming framework and a programming model; facilitating interfacing between the programming framework and the programming model, wherein interfacing includes merging the programming model into the programming framework, wherein interfacing further includes integrating the programming framework with a distribution framework hosting the programming model; and calling on the distribution framework to schedule processing of a plurality of jobs based on the request.
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公开(公告)号：US20220414010A1
公开(公告)日：2022-12-29
申请号：US17704340
申请日：2022-03-25
Applicant: Intel Corporation
Inventor： Xiaodong Qiu , Yong Jiang , Changwon Rhee , Cui Tang , Shuangpeng Zhou , Lei Chen , Danyu Bi , Peiqing Jiang , Chengxi Wu
IPC: G06F12/084 , G06F9/48
Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.
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公开(公告)号：US20210035317A1
公开(公告)日：2021-02-04
申请号：US17072784
申请日：2020-10-16
Applicant: Intel Corporation
Inventor： Yi Wu , Shaojun Yao , Yong Jiang
IPC: G06T7/557 , H04N13/271 , H04N13/218
Abstract: A system for sub-pixel disparity estimation is described herein. The system includes memory circuitry to store image data and at least one processor to execute instructions to calculate a first disparity for a set of reference views. The reference views correspond to a first subset of views among a plurality of sub-aperture views represented in the image data. The at least one processor is to refine the first disparity to a second disparity for the reference views. The second disparity has higher precision than the first disparity. The at least one processor is to map the second disparity from the reference views to a second subset of views among the plurality of sub-aperture views different than the first subset of views.
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10.发明申请公开(公告)号：US20190355139A1
公开(公告)日：2019-11-21
申请号：US16463456
申请日：2016-12-23
Applicant: INTEL CORPORATION
Inventor： Yi Wu , Shaojun Yao , Yong Jiang
IPC: G06T7/557 , H04N13/271 , H04N13/218
Abstract: A system for sub-pixel disparity estimation is described herein. The system includes a plenoptic camera, a memory, and a processor. The memory is configured to store imaging data. The processor is \coupled to the memory and the plenoptic camera. The processor is to obtain a plurality of sub-aperture views, select a subset of sub-aperture views as reference views for a disparity calculation, and calculate an integer disparity for the reference views. The processor is also to refine the integer disparity to sub-pixel disparity accuracy for the reference views and propagate the sub-pixel disparity from the reference views to other views of the plurality of sub-aperture views.
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