公开(公告)号：US10210119B2

公开(公告)日：2019-02-19

申请号：US15454100

申请日：2017-03-09

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

IPC: G06F9/455 ,  G06F17/50 ,  G06F13/364 ,  G06F13/16 ,  G06F13/362 ,  G06F13/42

Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

公开(公告)号：US20160210381A1

公开(公告)日：2016-07-21

申请号：US14920445

申请日：2015-10-22

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

IPC: G06F17/50

CPC classification number: G06F13/364 ,  G06F13/1621 ,  G06F13/3625 ,  G06F13/4252 ,  G06F13/4256 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045

Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

Abstract translation: 验证硬件设计中仲裁器的操作。 仲裁器在多个时钟周期内接收多个请求，包括被监视的请求，并以优先顺序输出请求。 识别在每个时钟周期中由仲裁器接收和输出的请求。 然后，使用基于在每个时钟周期中输入到仲裁器并从仲裁器输出的请求而更新的计数器跟踪观察请求相对于仲裁器中的其他未决请求的优先级，以及识别由所述仲裁器接收的请求的相对优先级的掩码 仲裁者在同一个时钟周期。 使用断言来确认仲裁器的操作，该断言建立从仲裁器输出监视请求的计数器与时钟周期之间的关系。

公开(公告)号：US10359825B2

公开(公告)日：2019-07-23

申请号：US15351644

申请日：2016-11-15

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  John Alexander Osborne Netterville ,  Ashish Darbari

IPC: G06F17/50 ,  G06F1/28 ,  G06F1/3234 ,  G06F1/12

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

公开(公告)号：US20170205864A1

公开(公告)日：2017-07-20

申请号：US15351644

申请日：2016-11-15

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  John Alexander Osborne Netterville ,  Ashish Darbari

IPC: G06F1/28 ,  G06F1/12

CPC classification number: G06F1/28 ,  G06F1/12 ,  G06F1/3243 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/78 ,  Y02D10/152

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

公开(公告)号：US20170177521A1

公开(公告)日：2017-06-22

申请号：US15454100

申请日：2017-03-09

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F13/1621 ,  G06F13/3625 ,  G06F13/4252 ,  G06F13/4256 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045

Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

公开(公告)号：US09626465B2

公开(公告)日：2017-04-18

申请号：US14920445

申请日：2015-10-22

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

IPC: G06F17/50

CPC classification number: G06F13/364 ,  G06F13/1621 ,  G06F13/3625 ,  G06F13/4252 ,  G06F13/4256 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045

Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.