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    CHIP PACKAGE STRUCTURE
    1.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210183789A1

    公开(公告)日：2021-06-17

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    Chip package structure
    2.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11362045B2

    公开(公告)日：2022-06-14

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    Redistribution structure and forming method thereof
    4.
    发明授权
    Redistribution structure and forming method thereof 有权

    公开(公告)号：US11251115B1

    公开(公告)日：2022-02-15

    申请号：US17144144

    申请日：2021-01-08

    Applicant: Industrial Technology Research Institute

    Inventor： Shao-An Yan ,  Chieh-Wei Feng ,  Tzu-Yang Ting ,  Tzu-Hao Yu ,  Chien-Hsun Chu ,  Jui-Wen Yang ,  Hsin-Cheng Lai

    IPC: H01L23/498 ,  H01L21/48 ,  G06F30/3308 ,  G06F119/18

    Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1−(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

    Pixel structure and display panel
    5.
    发明授权
    Pixel structure and display panel 有权

    公开(公告)号：US10418435B2

    公开(公告)日：2019-09-17

    申请号：US15691755

    申请日：2017-08-31

    Applicant: Industrial Technology Research Institute ,  Intellectual Property Innovation Corporation

    Inventor： Tai-Jui Wang ,  Chieh-Wei Feng ,  Meng-Jung Yang ,  Wei-Han Chen ,  Shao-An Yan ,  Tsu-Chiang Chang

    IPC: H01L27/12 ,  H01L27/32

    Abstract: A pixel structure including a substrate, a power wire, a planarization layer, a drive circuit and a conductive structure is provided. The substrate has a layout area and a light-transmitting area located outside the layout area. The power wire is disposed on the layout area of the substrate. The power wire includes a shielding layer. The planarization layer is disposed on the substrate and covers the power wire. The drive circuit is disposed on the planarization layer and corresponds to the layout area. The drive circuit includes a first active device. The shielding layer overlaps with the first active device. The conductive structure is disposed in the planarization layer and distributed corresponding to the layout area. The power wire is electrically connected with the drive circuit through the conductive structure. A display panel is also provided.

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