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    Chip package structure
    2.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11362045B2

    公开(公告)日：2022-06-14

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    TRANSPARENT FILM HEATER
    4.
    发明申请
    TRANSPARENT FILM HEATER 有权

    公开(公告)号：US20220338309A1

    公开(公告)日：2022-10-20

    申请号：US17707974

    申请日：2022-03-30

    Applicant: Industrial Technology Research Institute

    Inventor： Li-Wei Yao ,  Min-Hsiung Liang ,  Hsiao-Fen Wei ,  Yu-Pei Chang ,  Te-Hsun Lin ,  Chih-Chia Chang ,  Yen-Shu Lee

    IPC: H05B3/84

    Abstract: A transparent film heater is provided, including a transparent conductive film, at least two main electrodes and at least four multiple electrodes. The transparent conductive film is disposed on a transparent substrate. At least two main electrodes are arranged on two sides of the transparent conductive film along an edge of the transparent conductive film. The at least four multiple electrodes are composed of a first pair of multiple electrodes and a second pair of multiple electrodes, and are arranged on the transparent conductive film. A first spacing region and a second spacing region are respectively located between adjacent end points of the two main electrodes along the edge of the transparent conductive film. The first pair of multiple electrodes are arranged in the first spacing region, and the second pair of multiple electrodes are arranged in the second spacing region.

    CIRCUIT APPARATUS, MANUFACTURING METHOD THEREOF AND CIRCUIT SYSTEM
    6.
    发明申请
    CIRCUIT APPARATUS, MANUFACTURING METHOD THEREOF AND CIRCUIT SYSTEM 有权

    公开(公告)号：US20230138696A1

    公开(公告)日：2023-05-04

    申请号：US17585588

    申请日：2022-01-27

    Applicant: Industrial Technology Research Institute

    Inventor： Hung-Hsien Ko ,  Yi-Cheng Lu ,  Heng-Yin Chen ,  Hao-Wei Yu ,  Te-Hsun Lin

    IPC: H05K1/02 ,  H05K1/16 ,  H05K1/03

    Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.

    CHIP PACKAGE STRUCTURE
    7.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210183789A1

    公开(公告)日：2021-06-17

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

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