公开(公告)号：US20210376954A1

公开(公告)日：2021-12-02

申请号：US17333365

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Wai Keung Frankie Chan ,  Klaus Scheibert ,  Harald Zweck

IPC: H04L1/00 ,  H04L1/20

Abstract: An apparatus for handling an incoming communication data frame containing a plurality of bits is provided. The apparatus may include a plurality of data matchers, each data matcher configured to compare a subset of the plurality of bits of the communication data frame with a predetermined data pattern of a plurality of data patterns and to provide a data matcher output to indicate the result of the data matcher comparison, a plurality of selectors, each selector configured to compare a subset of the data matcher outputs of the plurality of data matchers with a predetermined selection pattern of a plurality of selection patterns and to provide a selector output to indicate the result of the selector comparison, and a frame filter configured to transfer the incoming frame to application logic only if the selector outputs of the plurality of selectors match a predetermined filter pattern, and to also transfer the selector outputs of the plurality of selectors to the application logic.

公开(公告)号：US09672182B2

公开(公告)日：2017-06-06

申请号：US14464991

申请日：2014-08-21

Applicant: Infineon Technologies AG

Inventor： Axel Freiwald ,  Klaus Scheibert

IPC: G06F15/16 ,  G06F13/40 ,  G06F1/10 ,  G06F13/42 ,  H04L12/42

CPC classification number: G06F13/4068 ,  G06F1/10 ,  G06F13/4221 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used.

公开(公告)号：US20140019805A1

公开(公告)日：2014-01-16

申请号：US14027464

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Barnardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

IPC: G06F11/263

CPC classification number: G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract translation: 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

公开(公告)号：US11705987B2

公开(公告)日：2023-07-18

申请号：US17333365

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Wai Keung Frankie Chan ,  Klaus Scheibert ,  Harald Zweck

IPC: H04L1/20 ,  H04L1/00

CPC classification number: H04L1/0045 ,  H04L1/0061 ,  H04L1/201

Abstract: An apparatus for handling an incoming communication data frame containing a plurality of bits is provided. The apparatus may include a plurality of data matchers, each data matcher configured to compare a subset of the plurality of bits of the communication data frame with a predetermined data pattern of a plurality of data patterns and to provide a data matcher output to indicate the result of the data matcher comparison, a plurality of selectors, each selector configured to compare a subset of the data matcher outputs of the plurality of data matchers with a predetermined selection pattern of a plurality of selection patterns and to provide a selector output to indicate the result of the selector comparison, and a frame filter configured to transfer the incoming frame to application logic only if the selector outputs of the plurality of selectors match a predetermined filter pattern, and to also transfer the selector outputs of the plurality of selectors to the application logic.

公开(公告)号：US11308240B2

公开(公告)日：2022-04-19

申请号：US16051775

申请日：2018-08-01

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Rieger ,  Klaus Scheibert

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/60 ,  G09C1/00 ,  G06F7/58

Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.

公开(公告)号：US20190050601A1

公开(公告)日：2019-02-14

申请号：US16051775

申请日：2018-08-01

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Viola Reiger ,  Klaus Scheibert

IPC: G06F21/72 ,  H04L9/08 ,  G06F7/58

Abstract: A method for cryptographic data processing by means of a circuit comprises using a first circuit section to perform a first cryptographic operation in order to obtain first cryptographic data. The method further includes transmitting the first cryptographic data to a second circuit section via a transmission area of the circuit that physically separates the second circuit section from the first circuit section and whose resistance to attacks is at most as high as the resistance of the first circuit section. The method includes using the second circuit section to perform a second cryptographic operation using the first cryptographic data in order to obtain second cryptographic data.

公开(公告)号：US08799703B2

公开(公告)日：2014-08-05

申请号：US14027464

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

IPC: G06F11/00

CPC classification number: G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract translation: 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

公开(公告)号：US20160055114A1

公开(公告)日：2016-02-25

申请号：US14464991

申请日：2014-08-21

Applicant: Infineon Technologies AG

Inventor： Axel Freiwald ,  Klaus Scheibert

IPC: G06F13/40 ,  G06F1/10 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F1/10 ,  G06F13/4221 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used.

Abstract translation: 提出了用于在包括主设备和多个从设备的系统内的两个以上电子设备之间传送高速数据信号的方法和系统。 主设备和多个从设备通过高速接口之间的高速链路连接，从而形成闭环。 高速接口分别由主设备和多个从设备中的每一个组成。 主设备向每个从设备提供公共低频时钟信号，并且使用用于通过高速链路在主设备和多个从设备之间进行通信的高速接口通信方法。