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    SAFETY HYPERVISOR FUNCTION
    2.
    发明申请
    SAFETY HYPERVISOR FUNCTION 有权
    安全超级功能

    公开(公告)号：US20150242233A1

    公开(公告)日：2015-08-27

    申请号：US14206033

    申请日：2014-03-12

    Applicant: Infineon Technologies AG

    Inventor： Simon Brewerton ,  Glenn Farrall ,  Neil Hastie ,  Frank Hellwig ,  Richard Knight ,  Antonio Vilela

    IPC: G06F9/455 ,  G06F9/30 ,  G06F13/28

    CPC classification number: G06F9/45558 ,  G06F9/30043 ,  G06F13/28 ,  G06F21/71 ,  G06F21/85 ,  G06F2009/45583 ,  G06F2009/45587

    Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

    Abstract translation: 本公开涉及用于定义用于控制分布式存储器访问保护系统的处理器安全特权级别的系统和方法。 更具体地，用于在计算机处理系统中访问总线的安全管理程序功能包括用于访问系统存储器的诸如计算机处理单元（CPU）或直接存储器访问（DMY）的模块以及用于存储安全性的存储单元 代码，如处理器状态字（PSW）或配置寄存器（DMA（REG））。 该模块将安全代码分配给处理事务，并且安全代码在模块访问总线时可见。

    METHOD AND SYSTEM FOR FAULT CONTAINMENT
    4.
    发明申请
    METHOD AND SYSTEM FOR FAULT CONTAINMENT 有权
    故障容器的方法和系统

    公开(公告)号：US20140337670A1

    公开(公告)日：2014-11-13

    申请号：US14337699

    申请日：2014-07-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Antonio Vilela ,  Andre Roger

    IPC: G06F11/07

    CPC classification number: G06F11/0763 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/1695

    Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

    Abstract translation: 实施例涉及用于系统中的错误容纳的系统和方法，包括通过多个处理单元处理输入信号来检测错误，以及延迟处理单元的至少一个输出信号，以在检测到错误的情况下使得在 处理单元的至少一个输出信号将导致错误传播通过系统。

    System and Method of High Integrity DMA Operation
    7.
    发明申请
    System and Method of High Integrity DMA Operation 有权
    高完整性DMA操作的系统和方法

    公开(公告)号：US20150039944A1

    公开(公告)日：2015-02-05

    申请号：US13957851

    申请日：2013-08-02

    Applicant: Infineon Technologies AG

    Inventor： Antonio Vilela ,  Simon Cottam

    IPC: G06F11/07

    CPC classification number: G06F11/0772 ,  G06F11/16 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/167 ,  G06F11/1675 ,  G06F11/2221 ,  G06F11/277 ,  G06F2201/845

    Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

    Abstract translation: 用于直接存储器访问（DMA）操作的系统和方法提供接收DMA请求者，将接收的DMA请求者分配给多个DMA引擎中的一个或多个以用于处理所接收的DMA请求者，并且如果所接收的DMA请求者之一是 将所述安全请求者分配给所述多个DMA引擎中的至少两个DMA引擎以处理所述安全请求者，禁用用于将所述至少两个DMA引擎的至少一个DMA引擎耦合到存储器的总线接口，将所述至少两个DMA引擎的输出进行比较 所述至少两个DMA引擎，并且如果所述至少两个DMA引擎的输出的比较彼此不同，则产生错误消息。

    METHODS AND SYSTEMS FOR MEASURING I/O SIGNALS
    8.
    发明申请
    METHODS AND SYSTEMS FOR MEASURING I/O SIGNALS 有权
    测量I / O信号的方法和系统

    公开(公告)号：US20140019805A1

    公开(公告)日：2014-01-16

    申请号：US14027464

    申请日：2013-09-16

    Applicant: Infineon Technologies AG

    Inventor： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Barnardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

    IPC: G06F11/263

    CPC classification number: G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

    Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

    Abstract translation: 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

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