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公开(公告)号：US09916278B2
公开(公告)日：2018-03-13
申请号：US14848472
申请日：2015-09-09
Applicant: Infineon Technologies AG
Inventor： Albert Missoni , Matthias Pichler
CPC classification number: G06F13/4291 , G06F1/12 , G06F1/3296 , G06F13/364 , H04L5/14
Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
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公开(公告)号：US20250147565A1
公开(公告)日：2025-05-08
申请号：US18937565
申请日：2024-11-05
Applicant: Infineon Technologies AG
Inventor： Armin Krieg , Christoph Saas , Matthias Pichler
Abstract: In accordance with one embodiment, a consuming device is provided, comprising a power supply for an authentication chip of a consumable component, wherein the internal resistance of the power supply is variable, a detection device configured to capture information about an operating state of the authentication chip for a plurality of values of the internal resistance of the power supply and to determine a dependence of the operating state of the authentication chip on the internal resistance of the power supply, and an authentication circuit configured to authorize the use of the consumable component by the consuming device based on the determined dependence.
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Patent Agency Ranking
公开(公告)号：US20200112932A1
公开(公告)日：2020-04-09
申请号：US16591864
申请日：2019-10-03
Applicant: Infineon Technologies AG
Inventor： Josef Gruber , Edmund Ehrlich , Matthias Emsenhuber , Juergen Hoelzl , Matthias Pichler
Abstract: A communication device having an antenna resonant circuit, an antenna driver which is configured to feed a carrier wave to the antenna resonant circuit, and a controller which is configured to detect that a synchronization period is imminent and is configured to control the antenna driver in such a way that the antenna driver feeds the inverted carrier wave to the antenna resonant circuit.
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公开(公告)号：US20160070672A1
公开(公告)日：2016-03-10
申请号：US14848472
申请日：2015-09-09
Applicant: Infineon Technologies AG
Inventor： Albert Missoni , Matthias Pichler
IPC: G06F13/42 , G06F1/12 , G06F1/32 , H04L5/14 , G06F13/364
CPC classification number: G06F13/4291 , G06F1/12 , G06F1/3296 , G06F13/364 , H04L5/14
Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
Abstract translation: 一种用于串行同步全双工总线系统的从设备，具有数据输入级，时钟输入级，接口逻辑，同步延迟触发器和数据输出级。 从设备使用纳米技术制造。 另外，一种用于操作从设备的方法。
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公开(公告)号：US10863467B2
公开(公告)日：2020-12-08
申请号：US16591864
申请日：2019-10-03
Applicant: Infineon Technologies AG
Inventor： Josef Gruber , Edmund Ehrlich , Matthias Emsenhuber , Juergen Hoelzl , Matthias Pichler
Abstract: A communication device having an antenna resonant circuit, an antenna driver which is configured to feed a carrier wave to the antenna resonant circuit, and a controller which is configured to detect that a synchronization period is imminent and is configured to control the antenna driver in such a way that the antenna driver feeds the inverted carrier wave to the antenna resonant circuit.
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公开(公告)号：US10467180B2
公开(公告)日：2019-11-05
申请号：US15919805
申请日：2018-03-13
Applicant: Infineon Technologies AG
Inventor： Albert Missoni , Matthias Pichler
IPC: G06F13/42 , G06F1/12 , G06F1/3296 , G06F13/364 , H04L5/14 , G06F1/10
Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
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公开(公告)号：US20180203820A1
公开(公告)日：2018-07-19
申请号：US15919805
申请日：2018-03-13
Applicant: Infineon Technologies AG
Inventor： Albert Missoni , Matthias Pichler
IPC: G06F13/42 , G06F1/32 , G06F13/364 , H04L5/14 , G06F1/12
CPC classification number: G06F13/4291 , G06F1/10 , G06F1/12 , G06F1/3296 , G06F13/364 , H04L5/14 , H04L5/1407
Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
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