公开(公告)号：US20180182651A1

公开(公告)日：2018-06-28

申请号：US15849801

申请日：2017-12-21

Applicant: Infineon Technologies AG

Inventor： Stuart Cardwell

IPC: H01L21/67 ,  H01R13/436 ,  H01L21/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/67144 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/73 ,  H01L2924/14 ,  H01R13/4365

Abstract: A method which comprises applying a common pressing force operative to interconnect an electronic chip with a connector body by an interconnect structure, and to contribute to a forming of the connector body.

公开(公告)号：US20210193560A1

公开(公告)日：2021-06-24

申请号：US16718443

申请日：2019-12-18

Applicant: Infineon Technologies AG

Inventor： Stuart Cardwell ,  Chee Yang Ng ,  Josef Maerz ,  Clive O'Dell ,  Mark Pavier

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.

公开(公告)号：US10319620B2

公开(公告)日：2019-06-11

申请号：US15849801

申请日：2017-12-21

Applicant: Infineon Technologies AG

Inventor： Stuart Cardwell

IPC: H01L21/60 ,  H01L21/67 ,  H01R13/436 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768 ,  H01L21/477

Abstract: A method which comprises applying a common pressing force operative to interconnect an electronic chip with a connector body by an interconnect structure, and to contribute to a forming of the connector body.

公开(公告)号：US11848257B2

公开(公告)日：2023-12-19

申请号：US17411633

申请日：2021-08-25

Applicant: Infineon Technologies AG

Inventor： Paul Westmarland ,  Stuart Cardwell

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49568

Abstract: A package is disclosed. In one example, the package comprises a carrier, a semiconductor chip having a first connection area at which the semiconductor chip is mounted at a first vertical level on or above the carrier, and a connection body. The semiconductor chip is bent to thereby be connected at a second connection area of the semiconductor chip at a second vertical level, being different from the first vertical level, with the connection body.