公开(公告)号：US20240145410A1

公开(公告)日：2024-05-02

申请号：US18404708

申请日：2024-01-04

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US12014996B2

公开(公告)日：2024-06-18

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US20210407932A1

公开(公告)日：2021-12-30

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/762

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US12154898B2

公开(公告)日：2024-11-26

申请号：US17133024

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Avyaya Jayanthinarasimham ,  Brian Greene ,  Suresh Vishwanath

IPC: H01L27/07 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.