公开(公告)号：US11901347B2

公开(公告)日：2024-02-13

申请号：US16887339

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Tahir Ghani

IPC: H01L25/18 ,  H01L23/00 ,  H01Q1/24

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2924/1436 ,  H01Q1/24

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

公开(公告)号：US12170273B2

公开(公告)日：2024-12-17

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US20240145410A1

公开(公告)日：2024-05-02

申请号：US18404708

申请日：2024-01-04

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US11817442B2

公开(公告)日：2023-11-14

申请号：US17114700

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L25/18 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US12014996B2

公开(公告)日：2024-06-18

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/58 ,  H01L27/12

CPC classification number: H01L23/564 ,  H01L21/76251 ,  H01L23/562 ,  H01L23/585 ,  H01L27/1203

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US20210375849A1

公开(公告)日：2021-12-02

申请号：US16887339

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Tahir Ghani

IPC: H01L25/18 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

公开(公告)号：US10811354B2

公开(公告)日：2020-10-20

申请号：US16306538

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Doug B. Ingerly

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/62

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20240030213A1

公开(公告)日：2024-01-25

申请号：US18474275

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L23/53223

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US11756886B2

公开(公告)日：2023-09-12

申请号：US17114537

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/18 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US20220181313A1

公开(公告)日：2022-06-09

申请号：US17114700

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.