公开(公告)号：US09955605B2

公开(公告)日：2018-04-24

申请号：US15085951

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Karen Navarro Castillo ,  Casey G Thielen ,  Alfredo Cueva Gonzalez ,  Benjamin Lopez Garcia

IPC: H01R12/70 ,  H05K7/10 ,  H05K1/11 ,  H01R43/20 ,  H01R13/6471

CPC classification number: H05K7/1061 ,  H01L2924/00 ,  H01R12/7076 ,  H01R13/6471 ,  H01R43/205 ,  H05K1/111

Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.

公开(公告)号：US20170288327A1

公开(公告)日：2017-10-05

申请号：US15085951

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Karen Navarro Castillo ,  Casey G. Thielen ,  Alfredo Cueva Gonzalez ,  Benjamin Lopez Garcia

IPC: H01R12/70 ,  H01R43/20 ,  H05K7/10

CPC classification number: H05K7/1061 ,  H01L2924/00 ,  H01R12/7076 ,  H01R13/6471 ,  H01R43/205 ,  H05K1/111

Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.

公开(公告)号：US09113555B2

公开(公告)日：2015-08-18

申请号：US13725556

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Xiaoning Ye ,  Kai Xiao ,  Benjamin Lopez Garcia

IPC: H01R13/66 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/0228 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/162 ,  H05K2201/09636 ,  Y10T29/49147

Abstract: A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a capacitive coupler between the first contact and the second contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor from the first vertical conductor.

Abstract translation: 减少串扰的方法。 该方法可以包括在第一垂直导体上形成第一接触。 该方法可以包括在第二垂直导体上形成第二接触。 该方法可以包括在第一触点和第二触点之间形成电容耦合器，其中电容耦合器将消除来自第一垂直导体的在第二垂直导体处接收的串扰。