公开(公告)号：US20240260188A1

公开(公告)日：2024-08-01

申请号：US18159930

申请日：2023-01-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brian Mark Hostetler

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K1/0218 ,  H05K3/4038 ,  H05K2201/093 ,  H05K2201/09636 ,  H05K2201/10818 ,  H05K2201/10984

Abstract: An electronic device may comprise a printed circuit board (PCB) and a power source and processing circuitry mounted to the PCB. The PCB comprises one or more power planes and a plurality of power vias electrically connected to the power planes. The power sources are electrically connected to the power planes. The processing circuitry is electrically connected to the plurality of power vias through a plurality of interconnects. Respective diameters of the plurality of power vias vary based on location.

公开(公告)号：US20180310403A1

公开(公告)日：2018-10-25

申请号：US15493680

申请日：2017-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chad M. Albertson ,  Eric J. Campbell ,  Nicholas J. Ollerich ,  Christopher W. Steffen

IPC: H05K1/09 ,  H05K1/18 ,  H05K3/10 ,  H05K3/14 ,  H05K3/12 ,  H05K3/18 ,  H05K3/34

CPC classification number: H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/146 ,  H05K3/3405 ,  H05K3/3436 ,  H05K2201/09636 ,  H05K2201/09836 ,  H05K2201/09945 ,  Y10T29/49155

Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

公开(公告)号：US09958496B2

公开(公告)日：2018-05-01

申请号：US14838605

申请日：2015-08-28

Applicant: Oracle International Corporation

Inventor： Stephanie Moran ,  Michael C. Freda ,  Karl Sauter

IPC: G01R31/28 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  H05K1/16 ,  H05K3/00

CPC classification number: G01R31/2813 ,  H05K1/0266 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/167 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4679 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2203/166

Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.

公开(公告)号：US09936570B2

公开(公告)日：2018-04-03

申请号：US14570791

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Min Wang ,  Russell N. Shryock

IPC: H05K1/02 ,  H01P3/02 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

公开(公告)号：US09560741B2

公开(公告)日：2017-01-31

申请号：US14511397

申请日：2014-10-10

Applicant: Curtiss-Wright Controls, Inc.

Inventor： Michael Rose ,  Robert Sullivan

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

Abstract translation: 电路板包括多个层，第一和第二参考导电通孔在垂直方向上延伸穿过多个层的至少一部分，第一和第二信号导电通孔在垂直方向上延伸并且在水平方向间隔开 从所述第一和第二参考导电通孔穿过所述多个层的至少一部分，以及在所述第一和第二信号导电通孔之间沿垂直方向延伸的电介质区域。 空气通道在垂直方向上延伸穿过第一和第二信号导电通孔之间的电介质区域。 反焊盘在第一和第二参考导电通孔之间沿水平方向延伸，并且在水平方向上包围第一和第二信号导电通孔，空气通孔和电介质区域。

公开(公告)号：US20160316562A1

公开(公告)日：2016-10-27

申请号：US14694759

申请日：2015-04-23

Applicant: Dell Products L.P.

Inventor： Kevin Warren Mundt ,  Sandor Farkas ,  Bhyrav Mutnury

IPC: H05K1/11 ,  G06F1/16 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/114 ,  G06F1/185 ,  G06F1/20 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: A circuit board includes a board base with a first surface and a second surface that is located opposite the first surface. A plurality of first coupling pads are located on the first surface of the board base. A plurality of second coupling pads are located on the second surface of the board base. The first coupling pads and the second coupling pads define a coupling pad footprint. A breakout via system is included in the board base. The breakout via system includes a plurality of primary signal vias that are located in the board base and outside of the coupling pad footprint, a plurality of first primary signal via connections that extend between the primary signal vias and the plurality of first coupling pads, and a plurality of second primary signal via connections that extend between the primary signal vias and the plurality of second coupling pads.

Abstract translation: 电路板包括具有第一表面的板基座和与第一表面相对定位的第二表面。 多个第一耦合垫位于板基底的第一表面上。 多个第二耦合垫位于板基底的第二表面上。 第一耦合焊盘和第二耦合焊盘限定耦合焊盘覆盖区。 董事会成员包括一个突破性的系统。 突破通孔系统包括多个主要信号通孔，其位于板基底中并且位于耦合垫足迹外部，多个第一初级信号经由连接在第一信号通孔和多个第一耦合垫之间延伸，以及 经由连接的多个第二主信号，其在主信号通孔和多个第二耦合焊盘之间延伸。

公开(公告)号：US09258888B2

公开(公告)日：2016-02-09

申请号：US14205344

申请日：2014-03-11

Applicant: TRIPOD TECHNOLOGY CORPORATION

Inventor： Bo-Shiung Huang ,  Wei-Hsiung Yang ,  Han-Ching Shih ,  Cheng-Feng Lin

IPC: H01F5/00 ,  H01F27/28 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46 ,  H05K3/42 ,  H01F17/00 ,  H01F17/06

CPC classification number: H05K1/0271 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/029 ,  H05K2201/086 ,  H05K2201/09636 ,  H05K2203/1178 ,  Y10T29/49165

Abstract: A printed circuit board package structure includes a substrate having a first surface and a second surface, a ring-shaped magnetic element, an adhesive layer, conductive portions and conductive channels. The first and second surfaces respectively have first and second metal portions. A ring-shaped concave portion is formed on a position not covered by the first metal portions of the first surface. The ring-shaped magnetic element is placed in the ring-shaped concave portion. The adhesive layer covers the first metal portions and the ring-shaped magnetic element. The conductive portions are formed on the adhesive layer. The conductive channels penetrate the conductive portions, the adhesive layer, and the substrate, and are respectively located in an inner wall and outside an outer wall of the ring-shaped concave portion. Each of the conductive channels includes a conductive film electrically connects to the aligned conductive portion and second metal portion.

Abstract translation: 印刷电路板封装结构包括具有第一表面和第二表面的基板，环形磁性元件，粘合剂层，导电部分和导电通道。 第一表面和第二表面分别具有第一和第二金属部分。 在未被第一表面的第一金属部分覆盖的位置处形成环形凹部。 环形磁性元件放置在环形凹部中。 粘合剂层覆盖第一金属部分和环形磁性元件。 导电部分形成在粘合剂层上。 导电通道穿透导电部分，粘合剂层和基底，并且分别位于环形凹部的内壁和外壁外侧。 每个导电通道包括导电膜电连接到对准的导电部分和第二金属部分。

公开(公告)号：US20150022288A1

公开(公告)日：2015-01-22

申请号：US14509285

申请日：2014-10-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO ,  Satoshi ISHINO ,  Jun SASAKI

IPC: H01P3/00 ,  H01P3/08

CPC classification number: H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/082 ,  H01P3/085 ,  H01P5/028 ,  H05K1/0225 ,  H05K1/0251 ,  H05K2201/09245 ,  H05K2201/09336 ,  H05K2201/09636 ,  H05K2201/097

Abstract: A high-frequency signal line includes a body with a first layer level and a second layer level; a signal line including a first line portion provided at the first layer level, a second line portion provided at the second layer level, and a first interlayer connection connecting the first line portion and the second line portion; a first ground conductor including a first ground portion provided at the first layer level; a second ground conductor including a second ground portion provided at the second layer level; and a second interlayer connection connecting the first ground portion and the second ground portion. A distance between the first interlayer connection and the second interlayer connection is not less than a maximum distance between the first line portion and the first ground portion and is not less than a maximum distance between the second line portion and the second ground portion.

Abstract translation: 高频信号线包括具有第一层级和第二层级的主体; 信号线，包括设置在第一层级的第一线部分，设置在第二层级的第二线部分和连接第一线部分和第二线部分的第一层间连接; 第一接地导体，包括设置在第一层级的第一接地部分; 第二接地导体，包括设置在第二层级的第二接地部分; 以及连接所述第一接地部和所述第二接地部的第二层间连接。 第一层间连接和第二层间连接之间的距离不小于第一线部分和第一接地部分之间的最大距离，并且不小于第二线路部分和第二接地部分之间的最大距离。

公开(公告)号：US20140266549A1

公开(公告)日：2014-09-18

申请号：US14205344

申请日：2014-03-11

Applicant: TRIPOD TECHNOLOGY CORPORATION

Inventor： Bo-Shiung HUANG ,  Wei-Hsiung YANG ,  Han-Ching SHIH ,  Cheng-Feng LIN

IPC: H05K1/02 ,  H05K3/42 ,  H01F27/28

CPC classification number: H05K1/0271 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/029 ,  H05K2201/086 ,  H05K2201/09636 ,  H05K2203/1178 ,  Y10T29/49165

Abstract: A printed circuit board package structure includes a substrate having a first surface and a second surface, a ring-shaped magnetic element, an adhesive layer, conductive portions and conductive channels. The first and second surfaces respectively have first and second metal portions. A ring-shaped concave portion is formed on a position not covered by the first metal portions of the first surface. The ring-shaped magnetic element is placed in the ring-shaped concave portion. The adhesive layer covers the first metal portions and the ring-shaped magnetic element. The conductive portions are formed on the adhesive layer. The conductive channels penetrate the conductive portions, the adhesive layer, and the substrate, and are respectively located in an inner wall and outside an outer wall of the ring-shaped concave portion. Each of the conductive channels includes a conductive film electrically connects to the aligned conductive portion and second metal portion.

Abstract translation: 印刷电路板封装结构包括具有第一表面和第二表面的基板，环形磁性元件，粘合剂层，导电部分和导电通道。 第一表面和第二表面分别具有第一和第二金属部分。 在未被第一表面的第一金属部分覆盖的位置处形成环形凹部。 环形磁性元件放置在环形凹部中。 粘合剂层覆盖第一金属部分和环形磁性元件。 导电部分形成在粘合剂层上。 导电通道穿透导电部分，粘合剂层和基底，并且分别位于环形凹部的内壁和外壁外侧。 每个导电通道包括导电膜电连接到对准的导电部分和第二金属部分。

公开(公告)号：US08743555B2

公开(公告)日：2014-06-03

申请号：US13965412

申请日：2013-08-13

Applicant: Micron Technology, Inc.

Inventor： Houfei Chen ,  Shiyou Zhao

IPC: H05K1/18 ,  H05K3/02

CPC classification number: H05K1/0216 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09981 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract translation: 具有诸如印刷电路板的电源层的衬底包括至少一个噪声抑制结构，其被配置为抑制通过第一电力平面和第二电力平面中的至少一个传播的电波。 至少一个噪声抑制结构可以包括从第一电力平面大致朝向第二电力平面延伸的第一电力平面延伸部，以及从第二电力平面大致向第一电力平面延伸的第二电力平面延伸部。 用于抑制第一电力平面和第二电力平面中的至少一个中的噪声的方法包括在电力平面之间提供这种噪声抑制结构。