公开(公告)号：US20170288327A1

公开(公告)日：2017-10-05

申请号：US15085951

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Karen Navarro Castillo ,  Casey G. Thielen ,  Alfredo Cueva Gonzalez ,  Benjamin Lopez Garcia

IPC: H01R12/70 ,  H01R43/20 ,  H05K7/10

CPC classification number: H05K7/1061 ,  H01L2924/00 ,  H01R12/7076 ,  H01R13/6471 ,  H01R43/205 ,  H05K1/111

Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.

公开(公告)号：US10903828B2

公开(公告)日：2021-01-26

申请号：US15488343

申请日：2017-04-14

Applicant: Intel Corporation

Inventor： Karen Navarro Castillo ,  Scott M. Rider

IPC: H03K7/08 ,  G06F1/26 ,  H02M1/00 ,  H02M3/158

Abstract: Embodiments herein relate to multi-phase voltage regulator power phase duty cycle control in computer add-in cards. A computer add-in card may include a card body, a first power connector disposed on the card body, a second power connector, one or more multi-phase voltage regulators coupled with one or more of the first power connector and the second power connector, and a processor coupled with the one or more multi-phase voltage regulators, where the processor is to generate one or more power control signals and one or more of the one or more multi-phase voltage regulators is to adjust a duty cycle of one or more power phases in response to the one or more power control signals. In some embodiments, the power control signals may be serial voltage identification signals or may be provided over an inter-integrated circuit bus. Other embodiments may be described and/or claimed.

公开(公告)号：US09955605B2

公开(公告)日：2018-04-24

申请号：US15085951

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Karen Navarro Castillo ,  Casey G Thielen ,  Alfredo Cueva Gonzalez ,  Benjamin Lopez Garcia

IPC: H01R12/70 ,  H05K7/10 ,  H05K1/11 ,  H01R43/20 ,  H01R13/6471

CPC classification number: H05K7/1061 ,  H01L2924/00 ,  H01R12/7076 ,  H01R13/6471 ,  H01R43/205 ,  H05K1/111

Abstract: Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.