公开(公告)号：US20190155630A1

公开(公告)日：2019-05-23

申请号：US15735578

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Bing ZHU ,  Kai WANG ,  Peng ZOU ,  Fangjian ZHONG

IPC: G06F9/455 ,  G06F9/30

Abstract: A processing system includes a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID) and a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID and responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.

公开(公告)号：US20190108051A1

公开(公告)日：2019-04-11

申请号：US16148245

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455 ,  G06F9/50

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.

公开(公告)号：US20170262306A1

公开(公告)日：2017-09-14

申请号：US15118844

申请日：2015-09-25

Applicant: Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO ,  INTEL CORPORATION

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F9/5027 ,  G06F2009/45566 ,  G06F2009/4557 ,  G06F2009/45591

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.

公开(公告)号：US20220164293A1

公开(公告)日：2022-05-26

申请号：US17441214

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Adrian PEARSON ,  Bing ZHU ,  Elena AGRANOVSKY ,  Tomas WINKLER ,  Yang HUANG

IPC: G06F12/14

Abstract: Multi-mode protected memory in accordance with the present description includes a permanent mode and a transient mode of operation. In one embodiment of the permanent mode, an authentication key is programmable once and a write counter is not decrementable or resettable. In one embodiment of the transient mode, an authentication key may be programmed many times and a write counter may be reset many times. Other features and advantages may be realized, depending upon the particular application.