公开(公告)号：US20190155630A1

公开(公告)日：2019-05-23

申请号：US15735578

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Bing ZHU ,  Kai WANG ,  Peng ZOU ,  Fangjian ZHONG

IPC: G06F9/455 ,  G06F9/30

Abstract: A processing system includes a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID) and a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID and responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.

公开(公告)号：US20190051963A1

公开(公告)日：2019-02-14

申请号：US16164352

申请日：2018-10-18

Applicant: Intel Corporation

Inventor： Jingbo LI ,  Kai XIAO ,  Howard HECK ,  Kai WANG

IPC: H01P5/02 ,  H01B7/04 ,  H01R12/73 ,  H01P3/02

Abstract: In accordance with embodiments disclosed herein, there is provided a high-density low-loss cable and connector assembly. A cable assembly includes a first cable connector, a bulk cable section, and a first cable transition section. The bulk cable section includes a first plurality of conductive wires of a first wire thickness. The first cable transition section includes a second plurality of conductive wires that has a first distal end connected to the bulk cable section and a second distal end connected to the first cable connector. Each of the second plurality of conductive wires transitions from the first wire thickness at the first distal end to a second wire thickness that is less than the first wire thickness at the second distal end. Each of the second plurality of conductive wires in the first distal end is connected to a corresponding conductive wire of the first plurality of conductive wires.

公开(公告)号：US20240421025A1

公开(公告)日：2024-12-19

申请号：US18290289

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Lianchang DU ,  Jeffory L. SMALLEY ,  Srikant NEKKANTY ,  Eric W. BUDDRIUS ,  Yi ZENG ,  Xinjun ZHANG ,  Maoxin YIN ,  Zhichao ZHANG ,  Chen ZHANG ,  Yuehong FAN ,  Mingli ZHOU ,  Guoliang YING ,  Yinglei REN ,  Chong J. ZHAO ,  Jun LU ,  Kai WANG ,  Timothy Glen HANNA ,  Vijaya K. BODDU ,  Mark A. SCHMISSEUR ,  Lijuan FENG

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01R13/627

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

公开(公告)号：US20190108051A1

公开(公告)日：2019-04-11

申请号：US16148245

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455 ,  G06F9/50

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.

公开(公告)号：US20170262306A1

公开(公告)日：2017-09-14

申请号：US15118844

申请日：2015-09-25

Applicant: Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO ,  INTEL CORPORATION

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F9/5027 ,  G06F2009/45566 ,  G06F2009/4557 ,  G06F2009/45591

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.