公开(公告)号：US20190108051A1

公开(公告)日：2019-04-11

申请号：US16148245

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455 ,  G06F9/50

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.

公开(公告)号：US20170262306A1

公开(公告)日：2017-09-14

申请号：US15118844

申请日：2015-09-25

Applicant: Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO ,  INTEL CORPORATION

Inventor： Kai WANG ,  Bing ZHU ,  Peng ZOU ,  Manohar CASTELINO

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F9/5027 ,  G06F2009/45566 ,  G06F2009/4557 ,  G06F2009/45591

Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.

公开(公告)号：US20190155630A1

公开(公告)日：2019-05-23

申请号：US15735578

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Bing ZHU ,  Kai WANG ,  Peng ZOU ,  Fangjian ZHONG

IPC: G06F9/455 ,  G06F9/30

Abstract: A processing system includes a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID) and a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID and responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.

公开(公告)号：US20170301309A1

公开(公告)日：2017-10-19

申请号：US15641052

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Fenardi THENUS ,  Peng ZOU ,  Raghu Nandan CHEPURI ,  Henry K. KOERTZEN

IPC: G09G5/00 ,  H02M3/158 ,  H03K7/08 ,  G06F3/041 ,  H03K17/284 ,  H03K7/06 ,  H03K5/14 ,  H02M1/00

CPC classification number: G09G5/006 ,  G06F3/0412 ,  G09G2330/021 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2003/1586 ,  H03K5/14 ,  H03K7/06 ,  H03K7/08 ,  H03K17/284 ,  Y02B70/16

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.