公开(公告)号：US20200233814A1

公开(公告)日：2020-07-23

申请号：US16786815

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Farah E. FARGO ,  Mitchell DIAMOND ,  David KEPPEL ,  Samantika S. SURY ,  Binh PHAM ,  Shobha VISSAPRAGADA

IPC: G06F12/1027

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

公开(公告)号：US20190042145A1

公开(公告)日：2019-02-07

申请号：US15854357

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Binh PHAM ,  Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zeshan A. CHISHTI ,  Zhe WANG

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/0897

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.