公开(公告)号：US20220269641A1

公开(公告)日：2022-08-25

申请号：US17738625

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US20210034565A1

公开(公告)日：2021-02-04

申请号：US16926524

申请日：2020-07-10

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US10713209B2

公开(公告)日：2020-07-14

申请号：US16446470

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/00 ,  G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US08996757B2

公开(公告)日：2015-03-31

申请号：US13631956

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Paulette Thurston ,  Bruce A. Tennant

IPC: G06F3/00 ,  G06F17/50

CPC classification number: G06F17/5054

Abstract: A programmable link training and status state machine is disclosed. The programmable finite state machine includes extra states, or shadow states, which are strategically used to debug a system design or to accommodate unexpected behavior, such as when the specifications of the design change. The programmable finite state machine is thus a mechanism to design in correctable logic, enabling the logic to be corrected in silicon and used in succeeding iterations of a product line.

Abstract translation: 公开了可编程链路训练和状态状态机。 可编程有限状态机包括额外的状态或阴影状态，这些状态或阴影状态有策略地用于调试系统设计或适应意想不到的行为，例如当设计规格发生变化时。 因此，可编程有限状态机是一种在可校正逻辑中设计的机制，使得逻辑能够在硅中被校正并用于产品线的后续迭代。

公开(公告)号：US08958471B2

公开(公告)日：2015-02-17

申请号：US13843137

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bruce A. Tennant

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L5/1438 ,  H04L25/0272

Abstract: Requests are identified for equalization coefficients and a plurality of coefficient selections are tracked relating to the requests. A matrix is maintained within a grid space that is to represent the coefficients, the matrix representing one or more of the coefficient selections. The matrix is adjusted within the grid space to obtain an adjusted matrix that is to accommodate selection of a particular coefficient outside the matrix. A final coefficient can be selected based on the adjusted matrix.

Abstract translation: 针对均衡系数识别请求，并跟踪与请求有关的多个系数选择。 将矩阵维持在用于表示系数的网格空间内，矩阵表示一个或多个系数选择。 在网格空间内调整矩阵以获得调整后的矩阵，以适应矩阵之外的特定系数的选择。 可以基于经调整的矩阵来选择最终系数。

公开(公告)号：US20220012203A1

公开(公告)日：2022-01-13

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US11144492B2

公开(公告)日：2021-10-12

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US10606785B2

公开(公告)日：2020-03-31

申请号：US16171342

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20190303342A1

公开(公告)日：2019-10-03

申请号：US16446470

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US20190065426A1

公开(公告)日：2019-02-28

申请号：US16171342

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.