公开(公告)号：US20180373665A1

公开(公告)日：2018-12-27

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin LI ,  Changhong LIN ,  James A. McCALL ,  Harry MULJONO

IPC: G06F13/40 ,  H04B3/23 ,  G06F13/16 ,  G11C7/12 ,  G11C7/22

CPC classification number: G06F13/4072 ,  G06F13/1689 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  H04B3/231

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuity to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.