公开(公告)号：US20190102331A1

公开(公告)日：2019-04-04

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang LI ,  Yunhui CHU ,  Jun LIAO ,  George VERGIS ,  James A. McCALL ,  Charles C. PHARES ,  Konika GANGULY ,  Qin LI

IPC: G06F13/16 ,  G11C5/06 ,  G11C5/04 ,  G06F1/18 ,  H01R12/73

CPC classification number: G06F13/1694 ,  G06F1/185 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  H01R12/73

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US20180373665A1

公开(公告)日：2018-12-27

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin LI ,  Changhong LIN ,  James A. McCALL ,  Harry MULJONO

IPC: G06F13/40 ,  H04B3/23 ,  G06F13/16 ,  G11C7/12 ,  G11C7/22

CPC classification number: G06F13/4072 ,  G06F13/1689 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  H04B3/231

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuity to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

公开(公告)号：US20180189214A1

公开(公告)日：2018-07-05

申请号：US15396268

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： James A. MCCALL ,  Zhichao ZHANG ,  Qin LI ,  Xiang LI ,  John R. DREW

IPC: G06F13/40 ,  H01R12/72

CPC classification number: G06F13/4022 ,  G06F13/4068 ,  H01R12/721

Abstract: Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways. Other embodiments are described and claimed.