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公开(公告)号：US09766683B2
公开(公告)日：2017-09-19
申请号：US15270206
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , Sm M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
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公开(公告)号：US09477627B2
公开(公告)日：2016-10-25
申请号：US13727052
申请日：2012-12-26
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , SM M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。
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公开(公告)号：US09092632B2
公开(公告)日：2015-07-28
申请号：US13836092
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Allen R. Wishman , Sergiu D. Ghetie , Michael Neve De Mevergnies , Ulhas S. Warrier , Adil Karrar , Douglas R. Moran , Kirk Brannock
CPC classification number: G06F21/60 , G06F21/572 , G06F21/64 , G06F21/74 , G06F2221/2137
Abstract: A method, apparatus, machine-readable medium, and system are disclosed. In one embodiment the method includes a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.
Abstract translation: 公开了一种方法，装置，机器可读介质和系统。 在一个实施例中，该方法包括处理器。 处理器包括将计算机平台中的平台固件更新机制切换到计算机平台引导时的平台固件铠装技术（PFAT）模式。 计算机平台包括存储平台固件的平台固件存储位置。 该方法然后持续地锁定平台固件存储位置，以响应平台固件更新机制切换到PFAT模式。 当持续锁定时，只能在运行平台中的认证代码模块才允许平台固件存储位置写入，并且只有在平台固件更新机制解锁过程之后才能进行写操作。
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公开(公告)号：US20170010648A1
公开(公告)日：2017-01-12
申请号：US15270206
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , Sm M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。
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