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    Technology to facilitate rapid booting with high-speed and low-speed nonvolatile memory
    1.
    发明授权
    Technology to facilitate rapid booting with high-speed and low-speed nonvolatile memory 有权

    公开(公告)号：US10474473B2

    公开(公告)日：2019-11-12

    申请号：US15484513

    申请日：2017-04-11

    Applicant: Intel Corporation

    Inventor： Michael A. Rothman ,  Vincent J. Zimmer ,  Giri P. Mudusuru ,  Jiewen Yao ,  Jie Lin

    IPC: G06F15/177 ,  G06F9/4401 ,  G06F3/06 ,  G06F21/57

    Abstract: A method for booting a data processing system (DPS) involves, during a boot process of the DPS, using a preliminary bootcode module from a low-speed nonvolatile memory (NVM) in the DPS to load a main bootcode module from a high-speed NVM in the DPS into a volatile random access memory (RAM) in the DPS, wherein the high-speed NVM supports a read speed that is faster than a maximum read speed of the low-speed NVM. The method also involves, during the boot process, after loading the main bootcode module from the high-speed NVM into the RAM, using the main bootcode module to boot the DPS to an operating system (OS). The method may also involve using the preliminary bootcode module to automatically determine whether the main bootcode module from the high-speed NVM has good integrity. Other embodiments are described and claimed.

    TECHNOLOGIES FOR PRE-MEMORY PHASE INITIALIZATION OF A COMPUTING DEVICE
    2.
    发明申请
    TECHNOLOGIES FOR PRE-MEMORY PHASE INITIALIZATION OF A COMPUTING DEVICE 审中-公开

    公开(公告)号：US20170147357A1

    公开(公告)日：2017-05-25

    申请号：US15426722

    申请日：2017-02-07

    Applicant: Intel Corporation

    Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

    IPC: G06F9/44 ,  G06F3/06

    CPC classification number: G06F9/4401 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F9/4403

    Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

    Technologies for pre-memory phase initialization of a computing device
    4.
    发明授权
    Technologies for pre-memory phase initialization of a computing device 有权
    用于计算设备的预存储器相初始化的技术

    公开(公告)号：US09563437B2

    公开(公告)日：2017-02-07

    申请号：US14318129

    申请日：2014-06-27

    Applicant: Intel Corporation

    Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

    IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44

    CPC classification number: G06F9/4401 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F9/4403

    Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

    Abstract translation: 用于预存储器相位初始化的技术包括具有具有高速缓存存储器的处理器的计算设备。 在初始化计算设备的主存储器之前，计算设备可以确定是否存在与处理器的高速缓冲存储器不同的临时存储器用于临时存储器访问。 响应于确定存在临时存储器，可以在初始化主存储器之前将基本输入/输出指令的一部分从计算设备的非易失性存储器复制到临时存储器以供执行。 响应于确定临时存储器不存在，计算设备还可以在处理器的初始化之前将处理器的高速缓冲存储器的一部分初始化为高速缓冲存储器作为用于临时存储器访问的RAM。 初始化之后，可以将主存储器配置为用于后续存储器访问。 描述和要求保护其他实施例。

    Technologies for pre-memory phase initialization of a computing device
    6.
    发明授权
    Technologies for pre-memory phase initialization of a computing device 有权

    公开(公告)号：US10592253B2

    公开(公告)日：2020-03-17

    申请号：US15426722

    申请日：2017-02-07

    Applicant: Intel Corporation

    Inventor： Giri P. Mudusuru ,  Rangasai V. Chaganty ,  Chasel Chiu ,  Satya P. Yarlagadda ,  Nivedita Aggarwal ,  Nuo Zhang

    IPC: G06F9/4401 ,  G06F3/06

    Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

    Technologies for improved hybrid sleep power management
    8.
    发明授权
    Technologies for improved hybrid sleep power management 有权

    公开(公告)号：US10198274B2

    公开(公告)日：2019-02-05

    申请号：US14670939

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Nicholas J. Adams ,  Erik C. Bjorge ,  Giri P. Mudusuru

    IPC: G06F1/32 ,  G06F9/4401 ,  G06F13/24 ,  G06F21/57 ,  G06F21/79

    Abstract: Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware environment, the computing device reserves a memory block for firmware use and copies platform wake code to a secure memory location, such as system management RAM (SMRAM). At runtime, an operating system may execute with the processor in protected mode. In response to a request to enter a sleep or suspend state, the computing device generates a system management interrupt (SMI). In an SMI handler, the computing device copies the wake code from SMRAM to the reserved memory block. The computing device resumes from the SMI handler to the wake code with the processor in real mode. The wake code enters the low-power idle state and then jumps to a wake vector of the operating system after receiving a wake event. Other embodiments are described and claimed.

    Techniques for coordinating device boot security
    10.
    发明授权
    Techniques for coordinating device boot security 有权

    公开(公告)号：US10747884B2

    公开(公告)日：2020-08-18

    申请号：US15778980

    申请日：2015-12-24

    Applicant: INTEL CORPORATION

    Inventor： Jiewen Yao ,  Vincent J. Zimmer ,  Wei Li ,  Rajesh Poornachandran ,  Giri P. Mudusuru

    IPC: G06F21/57 ,  G06F21/44 ,  G06F21/53 ,  G06F9/4401 ,  G06F9/54

    Abstract: Techniques for providing and maintaining protection of firmware routines that form part of a chain of trust through successive processing environments. An apparatus may include a first processor component (550); a volatile storage (562) coupled to the first processor component; an enclave component to, in a pre-OS operating environment, generate a secure enclave within a portion of the volatile storage to restrict access to a secured firmware loaded into the secure enclave; a first firmware driver (646) to, in the pre-OS operating environment, provide a first API to enable unsecured firmware to call a support routine of the secured firmware from outside the secure enclave; and a second firmware driver (647) to, in an OS operating environment that replaces the pre-OS operating environment, provide a second API to enable an OS of the OS operating environment to call the support routine from outside the secure enclave.

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