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    Circuits And Methods For Coherent Writing To Host Systems
    2.
    发明申请
    Circuits And Methods For Coherent Writing To Host Systems 有权

    公开(公告)号：US20220197852A1

    公开(公告)日：2022-06-23

    申请号：US17692031

    申请日：2022-03-10

    Applicant: Intel Corporation

    Inventor： Mohan Nair ,  Ishwar Agarwal ,  Ashish Gupta ,  Peeyush Purohit ,  Vijay Pothi Raj Govindaraj ,  Nitish Paliwal ,  Rahul Boyapati ,  Minjer Juan

    IPC: G06F15/173 ,  G06F9/50

    Abstract: A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

    TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT
    3.
    发明申请
    TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT 有权

    公开(公告)号：US20220197847A1

    公开(公告)日：2022-06-23

    申请号：US17674030

    申请日：2022-02-17

    Applicant: Intel Corporation

    Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

    IPC: G06F13/42 ,  G06F13/14

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

    PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory
    4.
    发明授权
    PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory 有权

    公开(公告)号：US11204867B2

    公开(公告)日：2021-12-21

    申请号：US15720648

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Ishwar Agarwal ,  Stephen R. Van Doren ,  Ramacharan Sundararaman

    IPC: G06F12/00 ,  G06F12/06

    Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space. The PCIe controller may include extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space. The extensions may include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI, a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI, host-bias-to-device-bias (HBDB) flip engine to enable the accelerator to flush a host cache line, and a QoS engine comprising a plurality of virtual channels.

    COHERENT MEMORY DEVICES OVER PCIe
    10.
    发明申请
    COHERENT MEMORY DEVICES OVER PCIe 审中-公开

    公开(公告)号：US20190102292A1

    公开(公告)日：2019-04-04

    申请号：US15720648

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Ishwar Agarwal ,  Stephen R. Van Doren ,  Ramacharan Sundararaman

    IPC: G06F12/06

    Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, having: a PCIe controller hub including extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space; wherein the extensions include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI; and a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.

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