公开(公告)号：US10579551B2

公开(公告)日：2020-03-03

申请号：US15855798

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Omid Azizi ,  Chandan Egbert ,  Amin Firoozshahian ,  David Christopher Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Ashok Raj ,  Alexandre Solomatnikov ,  Stephen Van Doren

IPC: G06F13/24 ,  G06F13/16 ,  G06F3/06

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

公开(公告)号：US11379592B2

公开(公告)日：2022-07-05

申请号：US16228121

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen Van Doren ,  Gilbert Neiger ,  Barry E. Huntley ,  Amy L. Santoni ,  Raghunandan Makaram ,  Hormuzd Khosravi ,  Siddhartha Chhabra

IPC: H04L29/06 ,  G06F21/60 ,  G06F12/0804 ,  G06F12/0864 ,  G06F9/455 ,  H04L9/08 ,  G06F12/0891

Abstract: An integrated circuit includes a core and memory controller coupled to a last level cache (LLC). A first key identifier for a first program is associated with physical addresses of memory that store data of the first program. To flush and invalidate cache lines associated with the first key identifier, the core is to execute an instruction (having the first key identifier) to generate a transaction with the first key identifier. In response to the transaction, a cache controller of the LLC is to: identify matching entries in the LLC by comparison of first key identifier with at least part of an address tag of a plurality of entries in a tag storage structure of the LLC, the matching entries associated with cache lines of the LLC; write back, to the memory, data stored in the cache lines; and mark the matching entries of the tag storage structure as invalid.

公开(公告)号：US11016894B2

公开(公告)日：2021-05-25

申请号：US15670171

申请日：2017-08-07

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Ishwar Agarwal ,  Stephen Van Doren

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0817

Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

公开(公告)号：US10437616B2

公开(公告)日：2019-10-08

申请号：US15396529

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh Sankaran ,  Stephen Van Doren

IPC: G06F9/455 ,  G06F9/50

Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.

公开(公告)号：US10216668B2

公开(公告)日：2019-02-26

申请号：US15087154

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC: G06F13/24 ,  G06F13/36 ,  G06F13/40 ,  G06F12/1027

Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US20230315632A1

公开(公告)日：2023-10-05

申请号：US17711471

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Philip Abraham ,  Stephen Van Doren ,  Ritu Gupta ,  Andrew Herdrich

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

公开(公告)号：US20240330053A1

公开(公告)日：2024-10-03

申请号：US18194408

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Philip Abraham ,  Priya Autee ,  Stephen Van Doren ,  Yen-Cheng Liu ,  Rajesh Sankaran ,  Kameswar Subramaniam ,  Ritesh Parikh

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/3009 ,  G06F9/5044

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

公开(公告)号：US11169929B2

公开(公告)日：2021-11-09

申请号：US15958591

申请日：2018-04-20

Applicant: Intel Corporation

Inventor： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/1027

Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US10990534B2

公开(公告)日：2021-04-27

申请号：US16264447

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Wei Chen ,  Eswaramoorthi Nallusamy ,  Larisa Novakovsky ,  Mark Schmisseur ,  Eric Rasmussen ,  Stephen Van Doren ,  Yen-Cheng Liu

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0802 ,  G06F12/02

Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

公开(公告)号：US20180189104A1

公开(公告)日：2018-07-05

申请号：US15396529

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh Sankaran ,  Stephen Van Doren

IPC: G06F9/50 ,  G06F9/455

Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.