公开(公告)号：US20250028532A1

公开(公告)日：2025-01-23

申请号：US18375488

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Jason AGRON ,  Andreas KLEEN ,  Ching-Tsun CHOU ,  Jonathan COMBS ,  Hongjiu LU ,  Jared Warner STARK, IV ,  Jeff WIEDEMEIER

IPC: G06F9/30

Abstract: Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.

公开(公告)号：US20240004662A1

公开(公告)日：2024-01-04

申请号：US17856978

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Amit GRADSTEIN ,  Regev SHEMY ,  Chitra NATARAJAN ,  Leonardo BORGES ,  Chytra SHIVASWAMY ,  Igor ERMOLAEV ,  Michael ESPIG ,  Or BEIT AHARON ,  Jeff WIEDEMEIER

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30025 ,  G06F9/30021

Abstract: Techniques for performing horizontal reductions are described. In some examples, an instance of a horizontal instruction is to include at least one field for an opcode, one or more fields to reference a first source operand, and one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least perform a horizontal reduction using at least one data element of a non-masked data element position of at least the first source operand and store a result of the horizontal reduction in the destination operand.

公开(公告)号：US20240004648A1

公开(公告)日：2024-01-04

申请号：US17856981

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Venkateswara Rao MADDURI ,  Jason BRANDT ,  Jeff WIEDEMEIER ,  Michael ESPIG

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30185 ,  G06F9/30098

Abstract: Techniques for vector unpacking are described. In some examples a single instruction is executed to perform vector unpacking. In some examples the instruction is to include one or more fields for an opcode, a destination operand identifier, a first source operand identifier, a second source operand identifier, and an immediate, wherein the opcode is to indicate execution circuitry is to interleave data elements from the identified first and second source operands according to an encoding of the immediate wherein the encoding of the immediate to include multiple controls with each control dictating what is to be written into a particular data element position of the identified destination operand;