公开(公告)号：US20180086627A1

公开(公告)日：2018-03-29

申请号：US15573342

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Kevin LAI LIN ,  Chytra PAWASHE ,  Raseong KIM ,  Ian A. YOUNG ,  Kanwal Jit SINGH ,  Robert L. BRISTOL

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0771 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.