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    DEVICE, METHOD, AND SYSTEM TO DETERMINE AN ACCESS TO A TRUSTED EXECUTION ENVIRONMENT
    1.
    发明公开
    DEVICE, METHOD, AND SYSTEM TO DETERMINE AN ACCESS TO A TRUSTED EXECUTION ENVIRONMENT 审中-公开

    公开(公告)号：US20240202314A1

    公开(公告)日：2024-06-20

    申请号：US18084428

    申请日：2022-12-19

    Applicant: Intel Corporation

    Inventor： Mona Vij ,  Dmitrii Kuvaiskii ,  Bin Xing ,  Krystof Zmudzinski ,  Scott Constable

    IPC: G06F21/53

    CPC classification number: G06F21/53 ,  G06F2221/034

    Abstract: Techniques and mechanisms for a processor core to execute an instruction for a hardware (HW) thread to have access to a trusted execution environment (TEE). In an embodiment, execution of the instruction includes determining whether any sibling HW thread, which is currently active, is also currently approved to access the TEE. TEE access by the HW thread is conditioned upon a requirement that any sibling HW thread is either currently inactive, is currently in the same TEE, or is currently approved to enter the TEE. In another embodiment, execution of another instruction, for the HW thread to exit the TEE, includes or otherwise results in system software being conditionally notified of an opportunity to wake up one or more sibling HW threads.

    Technologies for filtering memory access transactions received from one or more I/O devices
    2.
    发明授权
    Technologies for filtering memory access transactions received from one or more I/O devices 有权

    公开(公告)号：US11373013B2

    公开(公告)日：2022-06-28

    申请号：US16234871

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Luis Kida ,  Krystof Zmudzinski ,  Reshma Lal ,  Pradeep Pappachan ,  Abhishek Basak ,  Anna Trikalinou

    IPC: G06F21/78 ,  G06F21/44 ,  G06F21/85

    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.

    MECHANISM TO PREVENT SOFTWARE SIDE CHANNELS
    3.
    发明申请
    MECHANISM TO PREVENT SOFTWARE SIDE CHANNELS 审中-公开

    公开(公告)号：US20190251257A1

    公开(公告)日：2019-08-15

    申请号：US15897406

    申请日：2018-02-15

    Applicant: Intel Corporation

    Inventor： Francis McKeen ,  Bin Xing ,  Krystof Zmudzinski ,  Carlos Rozas ,  Mona Vij

    IPC: G06F21/55 ,  G06F21/53

    CPC classification number: G06F21/556 ,  G06F12/145 ,  G06F12/1491 ,  G06F21/53 ,  G06F2212/1052 ,  G06F2221/2149

    Abstract: A processor includes a processing core to identify a code comprising a plurality of instructions to be executed in the architecturally-protected environment, determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions, generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page, store, in the cache memory, the address translation data structure comprising the first address mapping, and execute the code by retrieving the first address mapping in the address translation data structures to be executed in the architecturally-protected environment, determine that a first physical memory page stored in the architecturally-protected memory matches a first virtual memory page referenced by a first instruction of the plurality of instructions, generate a first address mapping between a first address of the first virtual memory page and a second address of the first physical memory page, store, in the cache memory, an address translation data structure comprising the first address mapping, and execute the code by retrieving the first address mapping stored in the address translation data structure.

    EFFICIENT EXCEPTION HANDLING IN TRUSTED EXECUTION ENVIRONMENTS
    4.
    发明公开
    EFFICIENT EXCEPTION HANDLING IN TRUSTED EXECUTION ENVIRONMENTS 审中-公开

    公开(公告)号：US20230205869A1

    公开(公告)日：2023-06-29

    申请号：US17561412

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Scott Constable ,  Bin Xing ,  Yuan Xiao ,  Krystof Zmudzinski ,  Mona Vij ,  Mark Shanahan ,  Francis McKeen ,  Ittai Anati

    IPC: G06F21/53 ,  G06F9/30

    CPC classification number: G06F21/53 ,  G06F9/30145 ,  G06F9/30105

    Abstract: Systems, methods, and apparatuses relating efficient exception handling in trusted execution environments are described. In an embodiment, a hardware processor includes a register, a decoder, and execution circuitry. The register has a field to be set to enable an architecturally protected execution environment at one of a plurality of contexts for code in an architecturally protected enclave in memory. The decoder is to decode an instruction having a format including a field for an opcode, the opcode to indicate that the execution circuitry is to perform a context change. The execution circuitry is to perform one or more operations corresponding to the instruction, the one or more operations including changing, within the architecturally protected enclave, from a first context to a second context.

    Technologies for filtering memory access transactions received from one or more I/O devices
    8.
    发明授权
    Technologies for filtering memory access transactions received from one or more I/O devices 有权

    公开(公告)号：US11163913B2

    公开(公告)日：2021-11-02

    申请号：US16234871

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Luis Kida ,  Krystof Zmudzinski ,  Reshma Lal ,  Pradeep Pappachan ,  Abhishek Basak ,  Anna Trikalinou

    IPC: G06F21/78 ,  G06F21/44 ,  G06F21/85

    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.

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