公开(公告)号：US20230139346A1

公开(公告)日：2023-05-04

申请号：US17549685

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Liu LIU ,  Junchao DING ,  Yingming LIU ,  Jong Sun SEL ,  Yixin MA ,  Jinwoo LEE ,  Xi LIN

IPC: G11C16/04 ,  G11C8/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

公开(公告)号：US20230036595A1

公开(公告)日：2023-02-02

申请号：US17791176

申请日：2020-02-08

Applicant: Intel Corporation

Inventor： Deepak THIMMEGOWDA ,  Brian J. CLEEREMAN ,  Srivardhan GOWDA ,  Jui-Yen LIN ,  Liu LIU ,  Krishna PARAT ,  Jong Sun SEL ,  Baosuo ZHOU

IPC: H01L27/11582 ,  H01L27/11575 ,  G11C16/08

Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

公开(公告)号：US20220189976A1

公开(公告)日：2022-06-16

申请号：US17442582

申请日：2019-06-10

Applicant: INTEL CORPORATION

Inventor： Nanda Kumar CHAKRAVARTHI ,  David MEYAARD ,  Abhinav TRIPATHI ,  Liu LIU

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1157

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

公开(公告)号：US20220406352A1

公开(公告)日：2022-12-22

申请号：US17763172

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Liu LIU ,  Chuan SUN ,  Hong MA

IPC: G11C8/14 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.