公开(公告)号：US20170177528A1

公开(公告)日：2017-06-22

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4282

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US10191877B2

公开(公告)日：2019-01-29

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US10180927B2

公开(公告)日：2019-01-15

申请号：US15158265

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

IPC: G06F13/40 ,  G06F13/42

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

公开(公告)号：US20160267048A1

公开(公告)日：2016-09-15

申请号：US15158265

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract translation: 用于处理数据分组以用于通过不同相应通信协议的PHY层进行通信的设备。 在一个实施例中，该设备包括第一协议栈和第二协议栈，它们各自用于PCIe TM通信协议。 第一协议栈和第二协议栈可分别与设备的第一物理（PHY）层和第二PHY层接口。 第一协议栈和第二协议栈可以交换分组以促进通过第一PHY层和第二PHY层的通信。 在另一个实施例中，第一PHY层用于根据PCIe TM通信协议进行通信，第二PHY层用于根据另一种较低功率通信协议进行通信。