公开(公告)号：US20250112037A1

公开(公告)日：2025-04-03

申请号：US18374603

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Mark KOEPER ,  Andrew MOORE ,  Sreenivas KOSARAJU ,  Nicholas J. KYBERT ,  Mengcheng LU ,  Atul MADHAVAN ,  Sudipto NASKAR ,  Wei Z. QIU ,  Tiffany R. ZINK

IPC: H01L21/02 ,  H01L23/48 ,  H01L29/10 ,  H01L29/423

Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.

公开(公告)号：US20220068802A1

公开(公告)日：2022-03-03

申请号：US17133080

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Gokul MALYAVANATHAM ,  Philip YASHAR ,  Mark KOEPER ,  Bharath BANGALORE RAJEEVA ,  Krishna T. MARLA ,  Umang DESAI ,  Harry B. RUSSELL

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate, a second conductive interconnect line in a second ILD layer above the first ILD layer, and a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer. In another example, a method of fabricating an integrated circuit structure includes forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer, etching a hanging via that lands on the etch stop layer, and performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.