公开(公告)号：US20220172784A1

公开(公告)日：2022-06-02

申请号：US17107679

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Bayan NASRI ,  Tzu-Ning FANG ,  Rezaul HAQUE ,  Dhanashree R. KULKARNI ,  Narayanan RAMANAN ,  Matin AMANI ,  Ahsanur RAHMAN ,  Seong Je PARK ,  Netra MAHULI

IPC: G11C16/26 ,  G11C13/00

Abstract: A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

公开(公告)号：US20220366991A1

公开(公告)日：2022-11-17

申请号：US17321114

申请日：2021-05-14

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Tarek Ahmed AMEEN BESHARI ,  Matin AMANI ,  Narayanan RAMANAN ,  Arun THATHACHARY

IPC: G11C16/34 ,  G06F3/06

Abstract: An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.

公开(公告)号：US20220208286A1

公开(公告)日：2022-06-30

申请号：US17134010

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Tarek Ahmed AMEEN BESHARI ,  Shantanu R. RAJWADE ,  Matin AMANI ,  Narayanan RAMANAN

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.