公开(公告)号：US20250126869A1

公开(公告)日：2025-04-17

申请号：US18999923

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Subhash JOSHI ,  Michael J. JACKSON ,  Michael L. HATTENDORF

IPC: H10D64/01 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B10/00 ,  H10D1/47 ,  H10D30/01 ,  H10D30/62 ,  H10D30/69 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D62/822 ,  H10D62/834 ,  H10D64/23 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85 ,  H10D89/10

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

公开(公告)号：US20190165172A1

公开(公告)日：2019-05-30

申请号：US15859325

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Subhash JOSHI ,  Michael J. JACKSON ,  Michael L. HATTENDORF

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11 ,  H01L27/02 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

公开(公告)号：US20220344494A1

公开(公告)日：2022-10-27

申请号：US17849188

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Subhash JOSHI ,  Michael J. JACKSON ,  Michael L. HATTENDORF

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.