公开(公告)号：US10162761B2

公开(公告)日：2018-12-25

申请号：US15465560

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Sreenivas Mandava ,  Sarathy Jayakumar ,  Mohan J Kumar ,  Theodros Yigzaw ,  Ronald N Story

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/1009 ,  G06F9/26 ,  G06F9/30 ,  G06F13/24 ,  G06F13/364

Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

公开(公告)号：US11296921B2

公开(公告)日：2022-04-05

申请号：US15829935

申请日：2017-12-03

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J Kumar

IPC: H04L12/24 ,  H04L41/046 ,  G06F15/78 ,  H04L41/0896 ,  H04L9/08 ,  G06F30/34 ,  G06F13/42 ,  G06F21/76

Abstract: Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

公开(公告)号：US10423559B2

公开(公告)日：2019-09-24

申请号：US15274656

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Sheshaprasad G Krishnapura ,  Vipul Lal ,  Mohan J Kumar ,  Shaji Kootaal Achuthan ,  Ty H. Tang

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/16 ,  G06F13/36 ,  G06F13/42 ,  G06F11/30 ,  H04L29/06

Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.